搜索资源列表
DCM
- ISE实现DCM组建例化，得到3倍频时钟-ISE to achieve established cases of DCM, received 3 octave clock
dcm_test2
- xilinx fpga 倍频的例子，包含整个工程， 如果去用ISE 实现倍频，dcm 用法-xilinx s FPGA dcm example
DCM
- xilinx SP605开发板的DCM模块验证程序，coreGen工具生成DCM核，由DCM完成时钟分频、倍频、移相等操作-xilinx SP605 development board DCM module validation program, coreGen tool to generate nuclear DCM, completed by the DCM clock divider, frequency, and shift operations equal
BUFG_CLK2X_SUBM
- xilinx DCM 应用程序，完全可用-xilinx DCM applications, fully available
double_dcm
- 这个主要是在xilinx FPGA中双DCM连接的问题，这个问题网上资料很少，自己研究后并且仿真之后可以实现两个dcm的正常工作，实现倍频和时钟的反相-This is mainly the double in xilinx FPGA DCM connection problem which little information online, their own studies and simulation can be achieved after the normal work of the
DCM
- 详细介绍了基于XILINX公司FPGA时钟管理模块DCM的IP核生成和使用-xilinx ise DCM
TEST1
- Xilinx FPGA中DCM的用法，采用创建一个IP的方法。-Use DCM module in Xilinx FPGA.Creat a IP module to do it.
DCM
- fpga DCM使用教程 好几个文档 帮助您一次学会使用DCM-fpga the DCM using the tutorial a few documents to help you first learn to use the DCM
RELOJES
- SHOWS HOW TO CONFIGURE A DCM ON A SPARTAN FPGA
dac904_lock
- 采用xilinx的FPGA的DCM IP核进行开发的DA程序。-Using the xilinx FPGA-DCM IP core for the development of DA procedures.
sss
- 使用Verilog语言编写源代码.调用一些基本的IP核，如DCM模块、DDS模块ChipScope模块、乘法器模块等来实现调制.最后通过编程并利用FPGA板子实现AM、DBS、SSB的调制。-Using Verilog language source code. Invoke some basic IP cores, such as DCM module, DDS module ChipScope modules, multiplier module to achieve modulation.
CLK_GEN
- Xilinx FPGA时钟倍频电路，使用内部全局时钟、DCM，可参数化。-Clock Generater for Xilinx FPGA