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  1. rs_decoder_31_19_6.tar

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  2. Hard-decision decoding scheme Codeword length (n) : 31 symbols. Message length (k) : 19 symbols. Error correction capability (t) : 6 symbols One symbol represents 5 bit. Uses GF(2^5) with primitive polynomial p(x) = X^5 X^2 + 1
  3. 所属分类:VHDL编程

    • 发布日期:2014-01-22
    • 文件大小:13.91kb
    • 提供者:孟轲敏
  1. ViterbiDecodeK9R12HardDecision

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  2. viterbi 硬判决译码,基本实现了(2,1,9)卷积码的硬判决译码,用modelsim RTL仿真通过-hard-decision viterbi decoding, the basic realization of the (2,1,9) convolutional codes hard decision decoding, using modelsim RTL simulation through
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-03
    • 文件大小:12.73kb
    • 提供者:maojunling
  1. viterbi

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  2. 硬判决viterbi译码的硬件实现,通过verilog语言。采用回溯的方法。回溯深度为16.-Hard decision viterbi decoding in hardware, through the verilog language. A retrospective approach. Back depth is 16.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-29
    • 文件大小:90.27kb
    • 提供者:Fengxiaodong
  1. Design-Space-Exploration-of-Hard-Decision-Viterbi

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  2. Space Exploration of Hard-Decision Viterbi Decoding: Algorithm and VLSI Implementation
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-10
    • 文件大小:1.04mb
    • 提供者:saravanan
  1. viterbi_hard

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  2. (2,1,3)卷积码编码,硬判决译码;编码是matlab语言,译码是verilog语言-(2,1,3) convolutional code encoding, hard decision decoding coding is matlab language, decoding is verilog language
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-08
    • 文件大小:1.55mb
    • 提供者:刘星麟
  1. ldpc-decoder-code

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  2. Specify the decision method used for decoding as one of Hard decision | Soft decision . The default is Hard decision . When you set this property to Hard decision , the output is decoded bits of double or logical data type. When you set this property
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-13
    • 文件大小:2.18kb
    • 提供者:shankar.m
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