搜索资源列表
filter1300
- 用于TM1300/PNX1300系列DSP（主要用于视频处理）的各种滤波器源码，包括fir/iir,以及dct和idct等。-for TM1300/PNX1300 Series DSP (mainly for video processing), the filter All source code, including fir / IIR, and A1501 and IDCT so.
DCT_vhdl
- IDCT-M is a medium speed 1D IDCT core -- it can accept a continous stream of 12-bit input words at a rate of -- 1 bit/ck cycle, operating at 50MHz speed, it can process MP@ML MPEG video -- the core is 100％ synthesizable-IDCT-M is a medium speed
idct
- TI TMS320C6X系列DSP上DSP逆变换汇编代码-TI DSP TMS320C6X Series DSP inverse transform compiled code
D_IDCT
- 定点的idct源代码,自己编写的,对有需要的朋友应该有帮助.-spot idct source code, prepared by himself, in need of friends should help.
idct
- 基于恩智浦dsp芯片的idct源码，很实用
erweiDCT
- 一种改进的一维DCT方案设计与实现,采用VHDL实现,DCT以及IDCT
32dct1
- blackfin VisualDSP++ 下的音频32点IDCT变换汇编代码，可用于mp3解码器算法在bf53x系列环境下的优化。
BasedontheTMS320C64xhigh-definitionvideodecoderopt
- 论文设计了基于高性能通用DSP TMS320C64x的HDTV视频解码程序。该解码 程序针对C64的特殊架构做了多方面的优化。特别是对变长解码、IDCT和运动 补偿三个关键模块人工编写了汇编语言程序、调整了流水线操作。经过优化，显 著提高了解码效率。通过软件仿真可以得出如下重要结论：1）进行人工汇编优 化之后的程序效率相比于仅仅采用C语言优化之后的程序效率提高了将近七倍； 2）人工汇编优化之后，对标准清晰度视频进行实时解码时要求的时钟频率仅为 228.8MHz；3）对高清
8x8IDCT
- 8x8 iDCT verilog code 一次輸入八個點
idct_122700
- IDCT 反离散余弦变换原程序-IDCT inverse discrete cosine transform the original procedure
IDCT
- 用verilog HDL语言编写的IDCT程序，可以计算8*8的整形数矩阵，用ISE 9.1i编译通过-Using verilog HDL language of the IDCT program can calculate the number of 8* 8 matrix of plastic, with ISE 9.1i compiled by
attachments_2010_01_29
- dct and idct vhdl code
DCT_IDCT
- verilog code for DCT and IDCT (JPEG)
DCT_IDCT
- H264/AVS中的离散余弦变换DCT以及反离散余弦变换IDCT的Verilog代码-H264/AVS the discrete cosine transform and inverse discrete cosine transform DCT IDCT of Verilog code
dctidct
- dct and idct code for verilog
Axi_mux
- The elements come from the necessity of creating generic modules, in the verification phase, for this widely used protocol. These primitives are presented as a not compiled library written in SystemC where interfaces are the core of the lib
idct
- invert discret cosinus transformation VHDL code
exp10_3_BF537.7z
- ADSP-BF537 Experiment 10.3_BF537 2D DCT and IDCT using BF537 EZ-KIT
IDCT
- HEVC是正在研发的新一代视频编码标准。 本文面向HDTV应用，设计兼容HEVC标准的两位整数IDCT电路， 通过对IDCT的特点进行分析，完成了电路的架构设计, 采用较为节省面积的做法和流水线结构，并进行VerilogHDL代码设计-High Efficiency Video Coding(HEVC) is the currently developing video standard. In this article, a novel pipelined 2-D IDCT architect
DCT_IDCT
- DCT and Idct with vhdl and verilog