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xilinx_ise_12
- 最新xilinx_ISE-12.3 version License 扩展名.lic-xilinx_ISE-12.3 version License
eetop.cn_licgen_ise_13.1
- this the license genarator for xilinx ISE DESIGN SUIT 13.1 -this is the license genarator for xilinx ISE DESIGN SUIT 13.1
ddc_FPGA
- 简要介绍了数字下变频的设计，通过采用xilinx的ise软件，ipcore的调用实现-Briefly introduced the design of digital down conversion, through the use of ise the xilinx software, ipcore call the realization of
XILINX-ISE-MODELSIN-SE-Simulation
- Modelsim 10.0a 中建立 Xilinx ISE 13.1的仿真库及其之间调用设置详解。-Modelsim 10.0a create Xilinx 13.1 calls between the simulation library and its setting Detailed.
uart_a
- fpga 串口测试程序，应用语言为verilogHDL，开发环境为ISE 13.1-fpga serial test program
ISE-Design-Suite-13
- 这是ise10.1的实用说明，上面有好多的有用东西，希望对朋友们有所帮助-This is ise10.1 practical note, the above there are a lot of useful things, want to help friends
sp605_MIG_rdf0029_13.1_c
- ISE MIG（DDR3）使用方法，ISE版本为13.1-MIG user guide
xilinx-ise-13.1-operation-flow
- 此文档介绍了如何在xilinx ise 13.3的开发环境里面进行开发，并将程序下载到xilinx fpga里面-This document describes how to development, and download the program to the inside of xilinx fpga xilinx ise 13.3 development environment inside
my_uart2
- 基于FPGA的串口通信源代码。已经经过调试助手测试，-Release 13.2- WebTalk (O.61xd) Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Project Information -------------------- ProjectID=BFC2DD71D6FA404A87FDA640DB4B5999 ProjectIteration=14 WebTalk Sum
license
- Xilinx ISE13.1破解器，能够对XilinxISE13.1软件进行破解-Xilinx ISE 13.1 software cracker, generate license files, ISE13.1 crack
VmodCAM_Ref_HD Demo_13
- This project has dependencies in the 'digilent' VHDL library. For your convenience a local copy of these dependencies are included in the remote_sources directory. The VmodCAM_Ref_HD demo project was built around an Atlys+VmodCAM setup. The proj