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LCD.rar
- 有限状态机的设计——LCD显示控制实验，用VHDL编写程序，整片报告,Finite state machine design- LCD display control experiments, using VHDL programming, the whole report
fsm
- 有限状态机工作原理、设计方法、步骤等精要说明-Finite state machine working principle, design method, such as Essentials of steps to explain
state-machine-design
- 状态机设计的苦干个不错的例子，ＶＨＤＬ语言编写，相信会对verilog的学习者有帮助-State machine design a good example of hard work, VHDL language.Ｉthink it will help verilog learners
+VHDL
- 很详细用VHDL写的自动售货机程序有详细的说明和设计要求实现功能-Very detailed written using VHDL vending machine procedure is described in detail and design requirements for the realization of function
VHDL
- 各种有限状态机的设计。 VHDL源代码。 -All kinds of finite state machine design. VHDL source code.
ebook_verilog_fine_state_machine
- Designing a synchronous finite state machine (FSM) is a common task for a digital logic engineer. This paper discusses a variety of issues regarding FSM design using Synopsys Design Compiler. Verilog and VHDL coding styles are presented, and
virtual_machine_design
- 虚拟机的设计与实现-C_C++光盘资料.rar-Virtual Machine Design and Implementation-C_C++ CD-ROM. Rar
Design-and-implementation-of-RFID-Terminnal-based-
- 1、搭建了RFID手持移动终端的嵌入式Linux开发平台，基本工作包括硬件 平台的设计和软件平台的实现，其中软件平台的实现又包括Bootloader的移植、 内核的裁减与编译以及文件系统的制作三部分。 2、讨论并实现了RFID手持移动终端的若干基本功能模块，基本工作包括存 储管理模块的研究、人机交互模块的研究以及通讯模块的研究，其中每一模块又 包括硬件的设计和软件的实现，而软件的实现又包括驱动软件的开发和部分应用 软件接口的实现。所有这些模块功能独立，协同工作，共同构建了
Three-stage-state-machine
- 状态机是逻辑设计的重要内容，状态机的设计水平直接反应工程师的逻辑功底，所以许 多公司的硬件和逻辑工程师面试中，状态机设计几乎是必选题目。本章在引入状态机设计思想的基础上，重点讨论如何写好状态机。-State machine is an important part of logic design, state machine design engineers a direct response to the logic level of skills, so the company s ha
Sequence-Detector-State-Machine
- 状态机序列检测器设计，包含程序在内，该程序是检测1101-Sequence detection state machine design, including the program included, the program is to test 1101
Simulation-washing-machine-code
- 这是一个模拟洗衣机模型的设计代码，每段都有很好的注释，希望对你有所帮助。-This is a simulation model of washing machine design code, each has a very good note, I hope for your help.
6_VHDL-application-design
- VDHL应用实例，包括组合逻辑电路设计，时序逻辑电路设计，存储器设计，状态机设计 -VDHL application design samples, including combined logic design, timing logic design, memory design, and status machine design
state-machine-design
- Verilog and VHDL状态机设计，内含源代码，希望对大家有所帮助。-Verilog and VHDL state machine design, including source code, we want to help.
washing-machine-control
- 基于VHDL的洗衣机洗涤控制电路设计。洗衣机有强洗、标准、轻柔三种洗涤模式；三种洗涤定时；上电复位后的初始设定；启/停控制；洗涤定时精度。可在FPGA上实现。-VHDL-based washing machine control circuit design. Washing machine to wash with strong, standards, gentle washing three kinds of models three kinds of washing time afte
machine-design-
- 状态机实现序列检测器的设计，了解一般状态机的设计与应用-State machine to implement sequence detector design, understand the general state machine design and application
verilog-course-design
- 两个关于Verilog语言学习的课程设计，有要求、思路和代码，一个是芯片接口设计，一个是智能烧烤机设计-Two on the Verilog language learning course design, requirements, ideas and code, a chip interface design, a smart barbecue machine design
how-to-write-state-machine
- FPGA状态机设计中的问题，怎样写好三段式状态机，对于FPGA设计者很好的资料-FPGA state machine design issues, how to write a three-state machine, very good information for FPGA designers
State-machine-design-techniques
- 状态机设计-英文-如何编写状态机-case-State machine design techniques for Verilog and VHDL
State MAchine design for FPGA
- FPGA state machine design.
finite-state-machine-design
- 单片机有限状态机的设计技术相关文章资料，状态机设计可以降低循环时间-finite state machine design technongy