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Monolithic-machine-source-yard
- 通过软件的仿真,硬件的调试,实现串口数据的传输,开发环境包括C-C++与汇编语言.-through simulation software, hardware debugging, Serial data transmission, development environment, including C-C and assembly language.
state-machine
- 状态机，独热码实验，简单的Verilog语言设计For NJU，简单易行-State machine, one-hot code experiment, a simple Verilog language design For NJU, simple
state-machine-design
- 状态机设计的苦干个不错的例子，ＶＨＤＬ语言编写，相信会对verilog的学习者有帮助-State machine design a good example of hard work, VHDL language.Ｉthink it will help verilog learners
howwite_status_machine_with_Verilog
- 如何用verilog语言写好状态机的不错的文档，希望对大家有所帮助-How to use Verilog state machine language to write good documentation, I hope all of you to help
proteusofwaterheater
- proteus热水器仿真，包含电路硬件图及汇编语言，并在keil2中源代码通过-Proteus water simulation, including the hardware circuit diagram and assembly language, and in the source code through keil2
softdrink
- 自动售货机实现，采用VERILOG语言编写源码，与大家分享，共大家参考-Vending machine implementation, the use of language VERILOG source to share with you a total of U.S. reference
source_code
- 一个用c语言编写的自动售货机控制器源代码-A with c language source code for vending machine controller
FM_BPSK
- Send_message 数字发信机测试函数模块 功能：DDS语言调频发信机，中心载波频率可在2MHz ~ 10MHz之间任意切换， 显示当时刻载波中心频率；-The number of letters Send_message test function modules: DDS machine language FM sent a letter, the center carrier frequency 2MHz ~ 10MHz can switch back and forth b
mcs51huibianchengxu
- 汇编语言是面向机器硬件的语言，要求程序设计者 对MCS-51单片机具有很好“软、硬结合”功底。 介绍程序设计的基本知识及如何使用汇编语言来进 行基本的程序设计。 5.1 汇编语言程序设计概述 5.1.1 机器语言、汇编语言和高级语言-Assembly language is machine-oriented hardware language, ordering procedures for MCS-51 microcontroller designers have g
shiyanMUL
- 设计一台嵌入式CISC模型计算机（采用定长CPU周期、联合控制方式），并运行能完成一定功能的机器语言程序进行验证，程序功能可从以下3类中任选一个： ●输入1到8之间的任意一个整数N，求1到N之间的所有数的平方和并输出显示，和为单字长。 -To design a model of embedded CISC computer (using fixed-length CPU cycles, joint control mode), and run to complete a certai
Ultrasonic_Ranging
- 基于弹片机的超声波测距C语言程序；使用单片机的3.2口发送；3.5口接收-Based on Ultrasonic Ranging C shrapnel machine language program the use of SCM 3.2 to send 3.5 receiver
Automachine_project
- verilog 语言写的自动售货机程序，系IC课程设计代码，QUARTUS -verilog language written in a vending machine program, the Department of IC curriculum design code, QUARTUS II
stil_file_antomy
- 用于机台测试的STIL语言的详细语法描述-STIL test for the machine language syntax described in detail
statemachine
- 一个用vhdl语言写的交通灯控制的例子，可以很好的学习vhdl语言中状态机的使用。-Written in a language with vhdl traffic light control case study can be a good vhdl state machine language to use.
cop2000
- 模型机仿真的VHDL语言描述，在xilink9.1环境中实现。-VHDL simulation model of machine language to describe, in xilink9.1 environment implementation.
auto
- verlog语言编写的自动售货机源代码，可供初学者参考 -verlog vending machine language source code reference for beginners
verilog
- 用verilog语言进行状态机的时序与功能仿真-Verilog state machine language with timing and functional simulation
state-machine-code
- 用Altera Quartus II 的VHDL语言完成的状态机控制步进电机的程序员代码-The use of Altera Quartus II VHDL language to complete the state machine code programmer stepper motor control
state-machine-
- VHDL语言状态机的源程序，有助于学习VHDL语言的状态机-VHDL state machine of the source language to help learn the language of the state machine VHDL
Verilog-state-machine
- 状态机采用 VerilogHDL 语言编码，建议分为三个 always 段，本文档就是详述其原因-VerilogHDL language code using the state machine, the proposed section is divided into three always