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Embedded_MATLAB_Webinar_091307
- This file contains the material presented as the first Embedded MATLAB webinar on the MathWorks web site on September 13, 2007. It contains the PDF version of presentation slides and all necessary demonstration files (including MATLAB M-files and
DSP
- 数字信号处理课件++陈后金编.pdf DSP-DSP MATLAB
DSP_Applications_Using_C_and_the_TMS320C6x_DSK
- DSP Applications Using C and the TMS320C6x DSK (TI textbook)
noisecancellation
- Noise cancellation with adaptive filter.
fir
- RTDX与Matlab实现基于DSP的FIR滤波器设计.pdf-RTDX and Matlab for DSP-based FIR filter design. Pdf
GUI-MATLAB
- 精通GUI图形界面编程(MATLAB).pdf-Proficient in GUI graphical interface programming (MATLAB). Pdf
matlab_iir
- 用MATLAB辅助设计IIR数字滤波器.pdf 非常详细，值得参考-good！！！！！
MATLAB_DSP_guide
- DSP 在MATLAB环境下如何生成源码,用MATLAB仿真后,可以直接生成DSP代码,是很好的东西,对于DSP已经入门,准备入手算法的开发者有很大帮助.-DSP in the MATLAB environment, how to generate source code, with the MATLAB simulation, you can directly generate DSP code, is a good thing, for the DSP has been started, r
ss
- REMOVAL OF NOISE FROM ECG (ELECTROCARDIOGRAPHY) BY USING MATLAB. EEG (Electroencephalograph) recording from the scalp has biological artifacts and external artifacts. Biological artifacts, which are generated, can be EMG (Electromyography) sign
simulink-PDF-ebook
- simulink最全的外文书籍，工程仿真用，非常好，很全面-simulink most complete foreign language books, engineering simulation use, very good, very comprehensive
IIR_Filtering_C_Matlab
- 使用C和Matlab实现IIR滤波的设计。包中pdf是本程序实现功能的详细解释。-IIR filter design using C and Matlab. The pdf file in the .rar file is the detailed explanation of the function or purpose of this program.
PDF Documentation for Polyspace Code Prover
- PDF Documentation for Polyspace Code Prover
数字信号处理 基于计算机的方法 4版（中文版）
- 基于matlab的数字信号处理教程，对于入门学生可以提供帮助(Digital signal processing based on MATLAB)
1
- 数字通信同步技术的MATLAB与FPGA实现 Altera Verilog版.pdf(Synchronization technology of digital communication MATLAB FPGA Altera Verilog.pdf)
22
- 《数字滤波器的MATLAB与FPGA实现：Altera Verilog版》——杜勇六到九章pdf(Realization of digital filter with MATLAB and FPGA: Altera Verilog version)