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Qsys_nios2
- 本教程使用最新的Quartus 11.0sp1+Nios 11.0sp1开发工具。在最新的Quartus II软件中，使用了全新的Qsys进行SOPC系统的构建。 较之以前版本使用SOPC Builder构建有了很大的不同。 本教程为Altera最新的官方Tutorial。 一步步教你使用Qsys构建Nios II系统，并使用Nios II SBT开发应用程序。-This tutorial uses the latest Quartus 11.0sp1+ Nios 11.0sp1 d
esign_3c120_v110_qsys_revA
- 基于Altera Qsys vip_example_design_3c120_v110_qsys_revA-Based on Altera Qsys vip_example_design_3c120_v110_qsys_revA
led2
- nios ii 流水灯源程序，采用quartus ii 11.0,nios ii 11.0,qsys构建CPU，由本人亲自编写，并下载至电路板验证流水灯成功-nios ii water lights, quartus ii 11.0 nios ii 11.0 qsys build the CPU, I personally prepared and downloaded to the board verification of light water
MyC2Board_RS232_Test
- 这是一个Altera FPGA NIOS II RS232通讯程序。 在Quartus II工程中，用Qsys建立了一个NIOS II为核心的CPU系统，并挂接了一个RS232接口。 在software目录下，有三个工程，一个是用C++类包装的RS232类的Eclipse工程，一个是不用C++类包装的Eclipse工程，还有一个是用VC++2008编写的RS232测试工程。 VC++2008编写的工程运行在PC机上，与FPGA中的NIOS II通讯。 这个实验的主要目的是编写一个
qsys_design
- altera Qsys使用说明，陪了一个简单的例子，供参考-the altera Qsys Instructions accompany a simple example, for reference
tt_qsys_design
- Altera Qsys设计实例，软件需要QuartusII 11.0以上版本-Qsys Tutorial Design Example
DM9000A
- DM9000网卡驱动控制器（SOPC控制核），适用于quartus8.0以上版本的Qsys，添加方法与SOPC_Builder一样，可直接调用-DM9000 network card driver controller (SOPC control of nuclear), applicable to quartus8.0 above version of Qsys, adding the same way as SOPC_Builder， can be called directly
flash
- fpga nios ii vhdl qsys
Altera Qsys Design Tutorial
- The Qsys System Design Tutorial (PDF) provides step-by-step instructions to create and verify a design with the Qsys system integration tool in the Quartus® II software. This design example includes the system components to design a memory tester sys
i2c_4163okok
- 利用Altera的Qsys生成片上系统SOC，利用CPU进行I2C的配置电路。-Use of Altera s Qsys generation system on chip SOC, the use of the CPU I2C configuration circuitry.
youhua-Qsys-system-performance
- FPGA的Qsys系统的设计的优化设计中文资料-Qsys system optimization design of FPGA design Chinese data
sdram-uclinux
- 使用最新的系统搭建工具Qsys构建了包括sdram的nios2系统，编写了程序，并在de2上实现。-This file is used to drive the sdram for qsys users.
DE0_NANO_SDRAM_Nios_Test
- SDRAM Test by Niios II Many applications use SDRAM to provide temporary storage. In this demonstration hardware and software designs are provided to illustrate how to perform memory access in QSYS. We describe how the Altera’s SDRAM Controller IP is
DE0_NANO_SDRAM_Nios_Test
- SDRAM Test by Niios II Many applications use SDRAM to provide temporary storage. In this demonstration hardware and software designs are provided to illustrate how to perform memory access in QSYS. We describe how the Altera’s SDRAM Controller IP is
PCIe_Lab(ALTERA-V5PCIe)
- 这一设计实例深入浅出，介绍怎样产生一个Qsys子系统。 您将产生一个含有以下组成的Qsys系统:在Cyclone IV GX收发器入门套件上,设计带嵌入式收发器的Gen1×1硬核IP的 PCI Express IP编译器。 -Qsys system: the Cyclone IV GX Transceiver Starter Kit, designed with embedded transceivers Gen1 × 1 hard IP PCI Express IP compiler.
1hello
- sopc编程设计led，硬件软件系统都有，基于quartusii13.0的qsys-Sopc programming design of led, the hardware and software system, based on qsys quartusii13.0
2led
- sopc编程设计led，硬件软件系统都有，基于quartusii13.0的qsys 内容为控制led-Sopc programming design of led, the hardware and software system, based on qsys quartusii13.0
QSYS
- sopc系统，应用Qsys的应用程序，以便于新手学习(To achieve real-time operation of the system, to help newcomers just to understand)
niosii-triple-speed-ethernet-4sgx230-qsys-131
- Altera公司出的三速以太网例程，工程编译完了可以用niosii直接生成simple_socket_server，希望有用。(Altera company out of the three speed Ethernet routines, engineering finished, you can directly generate simple_socket_server using NiosII, I hope useful.)
i2c_master_ip_for_nios
- i2c master ip for altera nios, add in qsys