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sdmrbeh
- This code implements the behavioral modelling of a Moore type sequence detector to detect the sequence 1010. The code is a quartus project file
sdmrstruct
- This code implements the structural modelling of mealy type sequence detector to detect the sequence 1010. The code is a quartus project file
unishift
- An universal shift register performs the following tasks load, right shift ,left shift and parallel load as the selection inputs are 00,01,10,11 respectively. Such a register is implemented here in Quartus.
fir
- 16阶FIR VHDL程序并附带testbench,并有简单流水线设计!-16 Tap FIR vhdl code with testbench and pipelining design
electricdesign
- 用硬件电路实现简单音乐播放,基于Quartus平台。-The hardware circuit with simple music player, based on Quartus platform.
step
- 基于Quartus开发平台的3相6拍的步进电机-Quartus development platform based on the three-phase stepper motor 6 shooting. . . . . . . . . . . . .
FPGA
- 有关FPGA的一些资料以及个别源程序,编辑环境为quartus 主要有:电子设计竞赛优秀论文 ----相位测量仪 采用高速AD的存储示波器设计 基于FPGA的多种分频设计与实现 兼容ALTERA公司的USB Blaster下载线的原理图和PCB文件 FPGA与单片机的接口程序 FPGA的大量课件和实验源代码资料 FPGA七段译码器的设计 QuartusII学习资料-FPGA QuartusII
DisplayLCD
- 显示1602,将整数转化为BCD码 开发环境是Quartus II7.2-LCD1602 display develop software is Quartus II7.2
oc_i2c_master_v92
- I2C IP for Quartus V9.0 sp2, can used in SOPC builder.
oc_i2c_master_bit_ctrl_v92
- I2C IP for Quartus V9.0 sp2, can used in SOPC builder.
5minitersforQUARTUS
- 这压缩包是关于快速运用QUARTUS II的应用,很简单,初学者很有用。下载吧-5minitersforQUARTUS II is the instructions about application of QUARTUS ,it is useful for the news.
Synthesis_and_Scripting_Techniques_for_Designing_M
- quartus 使用分析与优化 实用 全面-Synthesis and scr ipting Techniques for Designing Multi-Asynchronous Clock Designs.pdf
dianziqin
- 这个程序是利用Quartus II编写的利用数控分频器设计硬件电子琴,主系统由3个模块组成,顶层设计文件内部有三个功能模块:SPEAKER.VHD 和TONE.VHD和NoteTabs.vhd。模块TONE是音阶发生器,模块SPEAKER中的主要电路是一个数控分频器,NOTETABS模块用于产生节拍控制和音阶选择信号。-This program is the use of Quartus II design prepared by the use of CNC divider hardware
vhdlcode
- VHDL code in ISE (for collecting the ADC samples from kit and for viewing final output)
AD7656_Tri
- 触发AD7656进行双路采样的触发控制模块 内附QUARTUS生成的bsf文件-AD7656 Dual Trigger to trigger the control module sample included QUARTUS generated bsf file
fpgatri
- FPGA三态门的VHDL实现。包括2种不同的实现方法。编译环境是Quartus-VHDL 3-state gate FPGA implementation. Including two kinds of different implementations. Build environment is Quartus
Quartus_ii_instruction
- 本文为Quartus 简明教程。以设计一个简单的LED7段译码器为例介绍使用Quartus设计的全过程。-This article Quartus simple tutorial. To design a simple example to explain LED7 segment decoder using the Quartus design process.
wishbone_i2c_master
- 本帖最后由 NovaCao 于 1-18-2009 18:02 编辑 使用Quartus II进行仿真 QQ:44425312 QQ群:50585234(群名称:FPGA4u) gtalk:fpgaforu@gmail.com 网站:www.fpga4u.com 淘宝网店:http://shop34914329.taobao.com/ 我们以一个计
iic.cx
- 本帖最后由 NovaCao 于 1-18-2009 18:02 编辑 使用Quartus II进行仿真 QQ:44425312 QQ群:50585234(群名称:FPGA4u) gtalk:fpgaforu@gmail.com 网站:www.fpga4u.com 淘宝网店:http://shop34914329.taobao.com/ 我们以一个计
calculator
- 课设一个,又臭又长,是一个用verilog编写的计算器,对应革新科技的某个sopc开发平台,键盘会扫描,七段二极管会译码且是并行输出,上传的是整个工程,在该开发平台上基本正常,主程序段编写的较为幼稚,希望大家多多扔玉。注:主程序段预计做八位计算器,后来因为实验平台只有六个数码管无奈之下后两位没接,主程序中的ac有问题,在开发平台上没效果,压缩包里的图是主程序在quartus下的仿真图,开发环境是quartus,不知应选哪项。最后:初次上传欢迎指正 -Set up a class, but als