搜索资源列表
dma_hussam
- verilog code for dma
fsk
- vhdl语言实现信号的fsk调制和解调。用 Quartus软件仿真-vhdl language signals fsk modulation and demodulation. Software simulation using Quartus
DE2_70_CAMERA_V1.0.3
- terasic 5mp camera also quartus 9.1 support
bujindianjikongzhi
- 在quartus II下用verilog编写的步进电机位置控制程序，其中包含7个子模块和1个顶层模块，本程序层次清晰、功能明确。乃个人收藏，推荐大家下载学习！-Verilog in quartus II, prepared under the stepper motor with position control program, which contains seven sub-modules, and a top-level module, the program-level clarity
FullAdder
- 要求在Quartus II软件，利用VHDL完成层次式电路设计，电路中的元件可以用VHDL设计也可以用库元件连线构成再封装。借助EDA工具中的综合器，适配器，时序仿真器和编程器等工具进行相应处理。输入方法不限制。适配采用Cyclone系列的EP1C6Q240C8。要求综合出RTL电路，并进行仿真输入波形设计并分析电路输出波形。要求采用层次式结构设计。-Quartus II software requires the use of VHDL complete hierarchical circui
Quartus7.0_licence
- A way to evalulate Quartus 7.0
counter999
- 采用quartus软件的verilog编程语言编写的计数器模块-Counter module
MultifunctionDigitalClock
- quartus软件环境下采用verilog语言编写的多功能数字钟-quartus software environment using verilog language multifunction digital clock
quartus2
- 学习这个文档可以亲送的操作quartus，可以进行vhdl的开发-This document can be sent to learn the operation of the pro quartus, can the development vhdl
dds
- DDS实验 matlab 与quartus 的完美结合-DDS experimental combination of matlab and quartus
shift8
- 用VHDL语言在QUARTUS环境下开发，功能是并串转换移位寄存器-Using VHDL language QUARTUS development environment, and the string conversion function is the shift register
cepin
- 频率计，在quartus环境下运行的程序，能测量信号的频率，信号的频率越大，测量的越准确-Frequency meter, in quartus environment running programs, and to measure the signal frequency, signal frequency is larger, the more accurate measurement
boxingfashengqi
- DDS波形发生器，能够产生方波和正弦波的双通道的波形发生器，在quartus环境下运行-DDS waveform generator to produce square wave and sine wave of dual-channel waveform generator, runs under the environment in quartus
pingpang
- 乒乓球游戏，由quartus ii图形化界面编程，也可以得到VHDL的程序-pingpong
chapter7
- VHDL 四位加法器 利用quartus II开发四位加法器，-VHDL comptur comparator_4
a
- 讲述了如何使用ModelSim与Quartus结合进行时序仿真 -Describes how to use ModelSim for timing simulation combined with the Quartus
p_s
- 用Verilog HDL语言进行串并转换，并通过Quartus Ⅱ 功能仿真验证-Series with the Verilog HDL language and converted, and through functional simulation Quartus Ⅱ
s_p
- 用Verilog HDL语言进行并串转换，并通过Quartus Ⅱ 功能仿真验证-With the Verilog HDL language and string conversion functions through simulation Quartus Ⅱ
kbmjsq
- 用Verilog HDL语言实现可变模计数器的功能，并通过Quartus Ⅱ 功能仿真验证-Variable with the Verilog HDL language to counter the function module and function through simulation Quartus Ⅱ
zmstz
- 用Verilog HDL语言实现正码速调整的功能，并通过Quartus Ⅱ 功能仿真验证-Verilog HDL language used is code rate adjustment function, and functional simulation by Quartus Ⅱ