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Counter
- 计数器 QuartusⅡ 10进制计数器 CLKIN为时钟输入端，CLR为清零端，Y[3..0]为四位二进制输出（BCD 码形式），CLKOUT为10进制计数器进位输出端 -Counter
clock
- 多功能数字钟，、在Quartus 2环境中编译通过； 4、仿真通过并得到正确的波形； 5、给出相应的设计报告 -clock
AMI_HDB3
- VHDL实现AMI码和HDB3码之间的相互转换，编译环境为Quartus II 6.1-HDB3 AMI code and VHDL code to achieve conversion between, the build environment for the Quartus II 6.1
NIOS_UART
- NIOS_LED现成fpgaNIOS系统源代码，运行环境quartus II -NIOS_LED ready fpgaNIOS system source code, operating environment quartus II
stratixIII_3sl150_dev_TSE_SGMII_v1
- 该程序实现altera开发板 stratix III 3S150通过以太网与pc之间通信。 使用Quartus II和Nios II 设计。 因为altera官方没有这块板子的正确网卡与pc通信的程序，-Overall This example works at 1000M/100M/10M Base SGMII mode on SIII 3S150 Kit. Designed by Quartus II/IP Cores/Nios II EDS v8.0 This is not
FPGA
- 本文采用FPGA来模拟实际的乒乓球游戏。本设计是基于Altera 公司的FPGA Cyclone II 芯片EP2C35 的基础上实现，运用Verilog HDL 语言编程，Quartus II 软件上进行编译、仿真，最终在Altera 公司的DE2 开发板上成功实现下载和调试-In this paper, FPGA to simulate the actual tennis game. The design is based on Altera' s FPGA Cyclone II EP
clock
- vhdl 数字钟工程文件夹 解压就可以用 quartus ii工程文件 -vhdl digital clock project folder can be used to extract the project file quartus ii
simulator_PCI
- about PCI connection in Quartus
int_div
- 基于VHDL的任意分频模块，利用Quartus II 9.0编译通过，并用示波器观察可行-VHDL-based modules of any division, the use of Quartus II 9.0 compiler, and the possible use of an oscilloscope
QuartusII_shuoming
- QuartusII简易操作说明 VHDL 仿真器 利用Quartus II 产生.VHO 和.SDO利用在sim_lib 目录中的APEX20K_ATOMs.VHD 和 APEX20K_COMPONENTS.VHD 文件 Verilog 仿真器 -QuartusII VHDL simulator simple instructions generated by Quartus II. VHO and. SDO use in sim_lib directory APEX20K_
quartustest
- FPGA quartus-II 测试程序！ -FPGA quartus-II test program! FPGA quartus-II test program!
uart_tx
- quartus.exe 环境下经过编辑和方针之后，作为FPGA器件的实验用串口发送数据驱动。-quartus.exe edited and policy environment after the experiment as the FPGA device to send data using serial port driver.
DDRSDRAMconclude
- DDR SDRAM技术总结 介绍DDR SDRAM的一些概念和难点 着重讲解主流DDRII的技术 最后结合硬件设计提出一些参考 -DDR SDRAM DDR SDRAM Technical Summary describes some of the concepts and difficult to explain the mainstream DDRII technology focused on the final hardware design combined with some ref
lcd1602_drive
- 简介 程序是用quartus.exe 开发的verilog 源程序 实现了lcd1602的驱动-About quartus.exe development program is implemented lcd1602 verilog source driver
uart_rx
- quartus.exe 环境下经过编辑和仿真之后，作为FPGA器件的实验用串口接收数据驱动。 -quartus.exe edited and policy environment after the experiment as the FPGA device to receive data-driven serial port.
eeprom_wr
- 本程序是quartus.exe 环境下经过编辑和仿真之后的eeprom中的i2C 通讯协议的驱动程序-This program is quartus.exe edited and simulation environment after the eeprom in the protocol driver i2C
gradtobin
- 格雷码转二进制的程序（verilog），经过验证quartus、8.1-grad to binary
ethmac
- ethmac IP CORE VHDL IN QUARTUS-ethmac IP CORE VHDL IN QUARTUSII
i2c
- I2C IP CORE Verilog quartus-I2C IP CORE Verilog quartusii
uart
- uart IP CORE Verilog quartus-uart IP CORE Verilog quartusii