搜索资源列表
wishbone
- wishbone IP CORE Verilog quartus-wishbone IP CORE Verilog quartusii
DE2_70_VGA
- 在Quartus中，用de2-70开发板下载实现视频图像处理！很值得认真学习！-In the Quartus in development board with the de2-70 image processing for video downloads! Is worthy of serious study!
I2C_bus
- 对I2C总线的简单操作,利用VHDL语言编写，在Quartus 8.1环境下测试通过，可以建立波形文件做仿真实验-very simple code foe I2C bus operation
disaplay_love
- 点阵显示桃心,利用VHDL语言编写，在Quartus 8.1环境下测试通过，可以建立波形文件做仿真实验-display love ,very funny
lcd_display
- 对LCD的简单操作,利用VHDL语言编写，在Quartus 8.1环境下测试通过，可以建立波形文件做仿真实验.液晶初学者必看-LCD operation ,just for the beginner of LCD.
PS_2_KEY
- 对PS2接口键盘的简单操作,利用VHDL语言编写，在Quartus 8.1环境下测试通过，可以建立波形文件做仿真实验-source code for PS2 keyboard
statemation-for-PWM-
- 基于状态机对步进电机的操作,利用VHDL语言编写，在Quartus 8.1环境下测试通过，可以建立波形文件做仿真实验-stepper motor based on ststemation
quartusii_handbook
- file contains the information about the quartus II tool
fpga
- TS流接收机上用的FPGA代码主要是把并行的TS流转成串行的ASI借口-TS stream FPGA code on the receiver is mainly used to flow into parallel serial ASI TS excuse
sdram_sv
- sdram在quartus下的VerilogHDL描述，准确的是SystemVerilog，已调试成功，不过还没利用突发传输功能，内含modulesim的仿真文件。-sdram VerilogHDL under the quartus descr iption is accurate SystemVerilog, has been commissioning successful, but not using burst transmission, the simulation file con
count10
- 在quartus环境下，开发的一个10位的计数器，性能可靠，可用作初学者的学习-Quartus environment in the development of a 10-bit counter, reliable performance, can be used for beginners to learn
Auto_elect_ticket_machines
- 数字逻辑的自动电子售票机的quartus编程。-Digital logic quartus automatic electronic vending machine programming.
sinbo
- 基于quartus，用VHDL写的正弦波发生器-Based quartus, written in sine wave generator with VHDL
LCD
- 基于altera cyclone3芯片，quartus软件lcd显示-lcd display
rdresult
- fpga 基础实验 代码 常用 附有quartus电路图 -fpga code commonly used in basic experimental schematic
quartusii_v10.1_handbook
- QuartusII 10.1的使用手册，非常详细，解决各种问题-QuartusII 10.1 user manual is very detailed and solve problems
32Kfft
- 32KFFT例程，适用于Quartus II 5.0 or later。- This design example requires the following software package: o Quartus II 5.0 or later o FFT MegaCore v2.1.3 o ModelSim version 6.0 or later
liangzhu
- 用Verilog语言编写梁祝歌曲，用quartus编译文件-Butterfly Lovers with Verilog language songs, compiled files with quartus
Timer
- 计时器的设计，在Quartus II上运行通过，FOR NJU Cser。使用了signaltap-The design of the timer, run by the Quartus II, FOR NJU Cser. Used signaltap
Counter
- 计时器的设计，在Quartus II上运行通过，简单易用，主要是For NJU CSers-The design of the timer, run by the Quartus II, easy to use, mainly For NJU CSers