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Rake_Receiver
- 用Verilog HDL语言实现一个Rake接收机的最大比合并准则，其中3路输入数据是并行相关输出-Verilog HDL language with a Rake receiver maximum ratio combining criteria, of which 3 related to the parallel input data is output
Rake-receive
- 本文介绍的一种基于多载波扩频通信的Rake接收机工作原理以及设计思想，并用FPGA技术加以实现-This article describes a multi-carrier spread spectrum based communication works as well as Rake receiver design and implementation with FPGA technology to
jieshouji
- 无线通信系统中最佳接收机的硬件描述语言，包括匹配滤波器、RAKE接收机的实现。-The realization of the RAKE receiver
rake_reciever
- wcama rake接收机的matlab仿真。可以作为项目设计的参考matlab代码-wcama rake receiver matlab simulation. Reference matlab code can be designed as a project