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RS232串口通信协议
- RS232串口通信协议，verilog实现，通过FPGA完全调通。,RS232 serial communication protocol, verilog achieved entirely through the FPGA transfer pass.
EPM240Prj.rar
- 这是一个verilog HDL 语言的例子，在CPLD器件EPM240上实现了 RS232协议、按键处理、LED数码管显示和每秒加1数码显示。使用quartus ii 7.0 以上打开.,This is an example of verilog HDL language in the CPLD device EPM240 achieved RS232 agreement, deal button, LED digital tube display and digital display plu
rs232
- 完整的RS232 Verilog源代码，支持波特率可调，支持调试命令，配合串口调试工具，可作为FPGA开发中的调试平台。-Full RS232 Verilog source code, support for baud rate is adjustable to support debugging command, with the serial debugging tools can be used as the debugging FPGA development platform.
rs232
- 用verilog实现的RS232时序控制，完整可以使用的-RS232 verilog implementation with timing control, you can use the full
c_FPGA
- RS232设计，硬件测试通过，VERILOG实现的，比较好的哦-RS232 design, hardware test, VERILOG realized, oh good
PS2RS232
- 这是关于PS2和rs232串口的代码，verilog的，是深入了解串口的好的学习实例。-good code about rs232 and ps2
uart1
- RS232(UART)串口传输，通过了FPGA验证功能正确-UART RS232 verilog HDL FPGA xilinx
RS232_NIOS_Verilog
- 5个文件，包含了RS232的nios实现和Verilog实现方式。其中,RS232的nios核实现只需要按照文件描述可以轻松实现^_^，个人比较推荐！RS232的Verilog实现需要编程，例程方便使用。RS232正在进一步学习中，有兴趣的可以探讨。-the realizition of rs232 interface by niosii uart ip core of Altera.it seems a most conveniet way.
RS232
- 实现FPGA的RS232串行通信，采用verilog语言编写，下载到芯片上就可以使用-FPGA implementation of the RS232 serial communication, using verilog language, can be downloaded to the chip using
rs232
- 本设计是PC和FPGA的串口通信的程序，用的是VERILOG语言，调试成功，用户可根据自己的项目稍作改动。-The design is a PC and the FPGA' s serial communication procedures, using a VERILOG language, debugged, the user can make a little change according to their own projects.
rs232
- 基于VERILog的RS232模块的程序，收发两个模块都有-The RS232 module based VERILog program, send and receive two modules have
rs232
- 使用VERILOG 代码实现的RS232 发送功能，接收一个字符马上回送回来-The RS232 using VERILOG code sending, receiving and sent back immediately return a character
rs232
- verilog语言编写，RS232通讯程序设计-verilog language, RS232 Communication Program Design
my_uart1_VERILOG_using-PLL
- Verilog uart example, RS232的Verilog例子。PC 发送一个字节（byte）到板子（FPGA），板子回发一个(byte+1).例子简洁，有注释。用到PLL，而且有3：2次数据采用-Verilog uart example，Verilog RS232 example，it s easy to understand, PC send 1 Byte RS232 code to FPGA, FPGA return 1 tht code，but Byte+1， Using P
async_transmitter
- RS232。串行通信接口RS232，verilog -failed to translate
RS232
- RS232与电脑串口的通信控制代码，verilog hdl代码，里面包括完整的ISE工程-RS232 and computer serial communication control code, verilog hdl code, which includes a complete ISE works
verilog串口收发模块程序
- 基于verilogHDL语言的RS232串口收发模块程序
rs232
- rs232串口通信实验4位的串口，verilog源代码。-rs232 serial communication experiment 4 serial, verilog source code
uart-verilog
- 经典rs232串口Verilog源代码，晶振可随意根据具体情况更改，代码风格非常清晰，明了！-Classic rs232 serial Verilog source code, the crystal can be altered depending on the circumstances, the code style is very clear, clear!
04_uart_test
- 串行通信程序，Verilog示例程序，通用RS232(Serial communication program)