搜索资源列表
ADS1252
- 内容为运用FPGA驱动ADS1252的工程文件，时钟频率为10M,内部使用了锁相环，可以自行调节采样频率。-FPGA-driven content for use ADS1252 project file, the clock frequency is 10M, internal use of the phase-locked loop, you can adjust their own sampling frequency.
Gen_R
- FPGA中将用采样点产生相关矩阵R的verilog代码-FPGA will generate correlation matrix R verilog code with the sampling points
AD9280
- 这是一个利用FPGA对模拟电压采集显示的例子，已经下板验证，效果很好！-This is an example about analog voltage sampling by FPGA, It is tested in the hongxin FPGA development board, The results are good!
MultHalfBand
- 多级半带滤波器的FPGA实现,采用6级滤波器实现的采样频率由3200Hz降为50Hz的抽取系统，前5级为半带滤波器,最后一级为普通FIR滤波器-Multi-level half-band filter FPGA, using six filters for sampling frequencies 50Hz down to 3200Hz extraction system for the front five and a half-band filter, the last stage of
ADS1278
- 这个程序实现AD采样芯片1278与FPGA的通信，按照datasheet上的时序编写。-This program implements 1278 AD sampling chip and FPGA communication, written in accordance with the timing on the datasheet.
AD_sampling
- 基于Verilog的AD采样FPGA程序,如果使用的话，FPGA接口重新设置即可-AD Sampling verilog program that is based on FPGA，if used，the IO Pins of FPGA should be redifined
ADS8509
- FPGA驱动高输入电压范围的ADS8509芯片，采样范围广，适合前端大信号处理-FPGA drive a high input voltage range ADS8509 chip, sampling a wide range, suitable for large front-end signal processing
ADVHDL
- 用fpga控制ad采集，用vhdl编写，可控制采样率-With fpga control ad acquisition, with vhdl written to control the sampling rate
dwn_sampler
- Multirate digital signal processing system which includes sampling rate conversion. This technique is necessary for systems with different input and output sampling rates, as the proposed multirate device is downsampler FPGA implementation of
adc0809_state
- 利用FPGA驱动DAC0832进行数据采样-Use FPGA drives DAC0832 sampling data
zonghe
- Quartus环境下编写的FPGA综合测试程序，能实现频率测量，数码管显示，12864液晶显示，1602液晶显示，点阵扫描显示，AD采样程序，DA输出电压程序，可以通过拨码开关控制上述功能的分别实现，还可以通过遥控器实现上述功能的控制实现。-Quartus environment prepared by the FPGA integrated test program, to achieve frequency measurement, digital display, 12864 LCD, 1
27_adda_test
- ADDA模块的代码，适用于黑金FPGA开发板，35M采样速率(The ADDA module code applies to the black gold FPGA development board, the 35M sampling rate)