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scramble.rar
- 通信用加扰码VHDL电路，解决光传输过程中的连零和连一码的出现。,Communication scrambling circuit VHDL Code
pcie_vera_tb_latest.tar
- FEATURES • 16 bit PIPE Spec PCI Express Testbench • Link training • Initial Flow Control • Packet Classes for easy to build PHY,DLLP and TLP packets • DLLP 16 bit CRC and TLP LCRC generation • Sequence Number
CCPCH_DPCH
- WCDMA扰码识别，VHDL语言编写-WCDMA scrambling code identification, VHDL language
82CPLD_raoma
- 基于CPLD的扰码与解扰码器的设计，扰码用M序列实现，m序列级数和频率可选-CPLD-based code scrambling code and de-scrambling device design, scrambling to achieve with the M series, m series progression and frequency of optional
bassicsofbissscrambling
- Basic of Biss scrambling
vhdl
- 该系统通过顶层模块，调用7底层模块实现。7大模块底层模块为：理想信源数据接收模块，理想信源数据缓存模块，LAPS成帧模块，加扰并发送LAPS帧模块，接收LAPS帧并解扰模块，接收LAPS帧数据缓存模块，解帧并发送数据给理想信源模块。另，还有一个fifo模块，以便两个缓存模块调用。-The system top-level module, called 7, the bottom module. Bottom-7 module module: the ideal source of data re
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- 2维随机矩阵置乱变换的周期及在图像信息隐藏的应用，作者：QQ 64134703 ，欢迎咨询-Two-dimensional random matrix scrambling transformation cycle and the application of information hiding in images, the author: QQ 64134703, welcomed the Advisory
216
- 基于信息熵的图像置乱程度评价方法,作者：QQ 64134703 ，电子毕业设计，欢迎咨询 -Entropy-based evaluation method of image scrambling, of: QQ 64134703, e-graduate design, please consult
Analysis-Of-The-Dvb-Common-Scrambling-Algorithm.r
- Analysis of the DVB Common Scrambling Algorithm (DVB-CSA) on FPGA implementation. Performance and Security.
scrambler
- example file Scrambling for DSP application book
scr_20
- 完成20位并行数据的伪随机序列扰码，配合解码部分，提高数字信道的SNR。已经通过综合仿真，并正在具体项目中运行，未发现任何缺点。-Completion of the 20 data-parallel pseudo-random sequence scrambling code with the decoding part, improve the SNR of the digital channel. Through integrated simulation, and run specific
descr_20
- 完成20位并行数据的伪随机序列解码，配合扰码部分，提高数字信道的SNR。已经通过综合仿真，并正在具体项目中运行，未发现任何缺点。-Completion of the 20 pseudo-random sequence of parallel data decoding, with part of the scrambling code, and to improve the SNR of the digital channel. Through integrated simulation, an
scramble
- 在quartusII上已经验证过，很有用的并行加扰程序，用的语言为verilog，需要的可以拿去-Has already been verified in quartusII useful parallel scrambling procedure, the language used for Verilog, need to take look at
QPSK
- qpsk调制的vhdl程序 扩频 加扰 解扩 解扰-the qpsk vhdl program spread spectrum modulation scrambling despreading descrambling
raoma
- MPSK的matlab仿真中复扰码的生成函数-MPSK matlab simulation of complex scrambling code generating function
jiarao4
- 加扰与解扰，VHDL实现。初始寄存器值为1产生的m序列。-Scrambling and descrambling, VHDL. Initial register value 1 of the m-sequences generated.
scramble_m_que
- 产生19级m序列，实现加扰和解扰的全过程。-19 m sequences, the scrambling process
test_scramb
- VHDL编写加扰和解扰程序，程序连在一起仿真正确，并通过下板子抓数据验证程序没问题-Write scrambling and descrambling program, VHDL program together properly simulation, and data validation procedures is caught by the board no problem
random
- 8位伪随机序列发生器。在通信加扰，序列检测中有很强的工程应用-8 pseudo-random sequence generator. In communications scrambling sequence detection has a strong engineering applications
scramblingadescrambling-vhdl
- scrambling and descrambling