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s2p.rar
- 串并转换功能，采用VERILOG语言编写，包括测试文件，与大家分享，供大家参考,SERDES function, the use of language VERILOG, including the test documents to share with you, for your information
DK-ECP3-SERDES-010
- 为verilog 的SERDES 使用程序。可以实现高速串行接口数据通信，时钟还原。-Verilog program for the use of the SERDES. For high-speed serial interface data communications, clock restoration.
RX
- 1路视频光端机的接收端，VHDL源码，使用全FPGA芯片的硬件，内建解帧、时钟、DESERDES-PDH a video of the receiving end, VHDL source code, use the whole FPGA chip hardware, built-in framing, clock, SERDES
TX
- 1路视频光端机的发射端，VHDL源码，使用全FPGA芯片的硬件，内建成帧、时钟、SERDES-The launch of a video PDH client, VHDL source code, use the whole FPGA chip hardware, built-in framing, clock, SERDES
elecfans.comMPSK
- 用VHDL实现的基带信号进行MPSK调制 及串并转换-Achieved using VHDL baseband MPSK signal modulation and SERDES
LVDS_Serdes_list_FPGA1
- FPGA之间的LVDS传输，采用serdes接口，传输速率达到400m-LVDS transmission between the FPGA using serdes interface, transfer rate up to 400m
keydisplay
- 单片机显示程序 采用键盘输入 定时器中断 串并转换 功能强大 有电路原理图 和源码-Single-chip display program using keyboard input timer interrupt powerful SERDES circuit schematic and source code
SerialtoParallel
- proteus仿真74164串并转换，显示跑马灯-proteus SERDES 74,164 simulation shows Marquee
chuankou
- 系统上电复位后，系统就处于等待状态，当K0到K7有按键动作时，单片机会将动作的按键号0到7串行发送到串并转换芯片74LS164中，芯片74LS164使74LS240驱动数码管显示按键所对应的按键号。-System power-on reset, the system in a wait state, when there are key K0 to K7 action, single-chip will be the key actions 0-7 serial number is sent t
74hc595
- 74HC595的汇编源代码,串并转换可省不少单片机口线.附595的规格书.-74HC595 compilation of source code, SERDES I can save a lot of single-chip line. 595 of the specifications attached.
74595
- 串并转换仿真，内有详细说明和仿真波形，能够成功运行-SERDES simulation
auk_sdsdi
- 用于FPGA设计的代码（Verilog代码），在FPGA设计中的高速串并转换，时钟提取，对齐处理等功能-for FPGA design ,written by Verilog HDL the functions include SERDES , CDR and so on
MAIN_RX_V10
- 8路视频光端机 接收侧 VHDL源码，使用了千兆以太网SERDES芯片，基于TBI接口的PCM视频传输。-8-Channel Video Optical Receiver side of VHDL source code, using the Gigabit Ethernet SERDES chip, based on the TBI interface PCM video transmission.
F7-2VT-1DR
- 2路视频光端机的，VHDL源码，使用全FPGA芯片的硬件，内建成帧、时钟、SERDES-2-way video PDH' s, VHDL source code, use the whole FPGA chip hardware, built-in framing, clock, SERDES
SERDES
- 基于Verilog的串并转换器的设计与实现，采用两种不同的方案来实现串并和并串转换的功能，并用ISE软件仿真以及chipscope的调试-Verilog-based serial and parallel converter design and implementation of two different programs to achieve the string and and and string conversion functions, and use the ISE softwa
SerDes-Architectures-and-Applications
- 关于lvds四种串行解串器的架构和应用的详细介绍和讨论，非常适合初学者使用-About lvds of four serial SerDes architecture and applications presented and discussed in detail, ideal for beginners
8b10btest
- lattice fpga serdes接口程序-lattice fpga serdes interface program
latticeECP3-serdes-test-code
- lattice ECP3系列高速FPGA serdes测试代码-lattice ECP3 series high speed serdes test code
LatticeECP3_SERDES_PCS_使用指南
- LatticeECP3 SERDES/PCS 使用指南(LatticeECP3 SERDES/PCS usage guide)
serdes verilog 仿真模型
- serdes verilog 仿真模型 20位输入输出