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TMS320C54x DSP 的cpu和外围设备
- 针对在FPGA中实现FIR滤波器的关键--乘法运算的高效实现进行了研究，给了了将乘法化为查表的DA算法，并采用这一算法设计了FIR滤波器。通过FPGA仿零点验证，证明了这一方法是可行和高效的，其实现的滤波器的性能优于用DSP和传统方法实现FIR滤波器。最后介绍整数的CSD表示和还处于研究阶段的根据FPGA实现的要求改进的最优表示。-view of the FPGA FIR filters achieve the key -- the multiplication Efficient Implem
audiodma
- DSP音频处理示例The benefits of real-time analysis provided by DSP/BIOS are often required in programs that were engineered without it. When the program is not built from the ground up using the DSP/BIOS kernel and real-time analysis features, the lack
CYPRESS_A3load
- a3load is 8051 firmware that can be used for uploading or downloading to EZ-USB RAM (internal or external). It implements the vendor specific command bRequest = 0xA3. The address to download/upload to/from is specified in the wValue field of t
linuxwifi
- We intend to develop a wifi enabled p2p file sharing system on a linux platform using jxta and java. The purpose is to build a system that can be ported to an embedded device at a later stage and be used for p2p file sharing using the 802.11b standar
dmx512_send
- 用C51编写的符合DMX512通信协议的发送程序,为从事或学习舞台灯光设计的朋友提供方便.-with C51 prepared by the communication protocol with the DMX512 this procedure, engaged in learning or stage lighting design for a friend of convenience.
jianbian001
- 本程序可用于LED灯饰或舞台灯的方案设计。-this procedure can be used for LED lighting or stage lights program design.
dmx512
- dmx 512协议接收程序,舞台灯光行业应用-agreement dmx 512 receiving procedures, stage lighting industry application
AD130_PLAY
- 用这个程序可以测试在每一阶段当前电池的电量，电流变化状况 （用在智能开发上，例如PocketPC,WinCE）-use of this procedure can be tested at every stage of the current battery capacity. Current conditions (used in the smart development, such as PocketPC, WinCE)
float_data_multiple_use_fixed_
- 采用fpga做小数运算的程序，使用了三级流水线技术，这是学习流水线和定点小数乘法很好的例子！,a program of float multiply, using 3-stage pipeline technology
2009-8-23LCD19264A_AVR_DS18B20
- 基于AVR的ATmega16/32的LCD19264液晶驱动，包含了精简的字符输出，增加DS18B20驱动融入了温度检测功。能特别指出的是，这个只是我的阶段性成功列子，今后会将继续完善并上传和大家一起分享,AVR-based LCD driver ATmega16/32 of LCD19264, including the streamlining of characters output, increasing the temperature detection DS18B20 drive i
Verilog
- Verilog三段式状态机描述，本章内容详细的介绍了Verilog三段式状态机描述，进一步加深对Verilog的认识-Verilog descr iption of three-stage state machine, this chapter introduces Verilog detailed descr iption of three-stage state machine, and further deepen the understanding of Verilog 朗读 显
pipelined-mips-cpu
- 用verilog语言描述了MIPS的5级流水线。-Language described by verilog MIPS 5-stage pipeline.
LHW214EH.pdf
- 功率型光电继电器,具5000耐压隔离电压.负边双向导通-The LHW214EH consists of an AlGaAs infrared light-emitting diode (LED) input stage optically coupled to a high-voltage output detector circuit. The detector consists of a high-speed photovoltaic diode array and driver ci
PipeLine.tar Verilog实现MIPS五段流水线
- Verilog实现MIPS五段流水线，22条指令（基本算术、移位和load、store指令），模块化设计，含注释-Verilog realization of five-stage pipeline MIPS 22 instructions (basic arithmetic, shift, and load, store instructions), modular design, with annotations
PIPE_LINING_CPU_TEAM_24
- 采用Quatus II编译环境，使用Verilog HDL语言编写实现了五段流水线CPU。 能够完成以下二十二条指令（均不考虑虚拟地址和Cache，并且默认为小端方式）： add rd,rs,rt addu rd,rs,rt addi rt,rs,imm addiu rt,rs,imm sub rd,rs,rt subu rd,rs,rt nor rd,rs,rt xori rt,rs,imm clo rd,rs clz rd,rs slt rd,rs,rt sltu rd,
cpu
- 5 stage pipeline CPU, verilog HDL code-5 stage pipeline CPU
DES_IP
- 有效的改进3-DES算法的执行速度，采用了多级流水线技术，设计了一种高速的硬件结构，使得原来需要48个时钟周期才能完成的运算，现在只需要一个时钟周期就可以完成。另外通过增加输入/输出的控制信号。使得该IP可以方便的集成到SOC中，大大缩短了SOC的设计周期。-Effective 3-DES algorithm to improve the implementation of speed, multi-stage pipeline technology, designed a high-speed
pipeline
- 用Quartus II 设计的3级流水CPU，指令采用二次重叠执行方式-Quartus II design with three-stage pipeline CPU, instruction execution overlaps with the second time
Pipelined-MIPS
- MIPS架构5级流水线设计，支持常用的整数指令。-5-stage pipeline MIPS architecture designed to support common integer instructions.
LMF_single_stage
- Active shult filter is used to operate grid at unity power factor. Solar panels are used to fed grid as well as load. This is single stage configuration.