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syncup_dn
- VHDL CODE FOR SYNCHRONOUS UP/DOWN COUNTER
SyncounterFinal
- 在Xillinx ISE 平台上利用VHDL语言实现同步计数器,利用状态机实现,导入FPGA版点亮7段数码管并实现加、减计数功能。-The programme realizes a counter based on synchronous state machines, and it can be download to a FPGA chip.