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uvm
- the Universal Verification Methodology (UVM) for creating SystemVerilog testbenches.
uvm-1.1d.tar
- UVM World 官方发布的UVM（通用验证方法学）的源代码，基于SystemVerilog，用于ASIC Verification。2013-03最新发布版本uvm-1.1d.tar.gz-The UVM World official release of the source code of the UVM (Universal Verification Methodology), based on SystemVerilog for ASIC Verification. 2013-03
uvm
- UVM验证平台的介绍，在验证方面效率由于systemverilog。-UVM verification platform introduced in verification efficiency due systemverilog.
uart2bus_testbench_latest.tar
- uart2bus_testbench,uart测试平台，主要运用uvm验证方法学，对uart接口、systemverilog和uvm等ic开发和验证有一个初步了解和掌握。-Uart2bus_testbench, uart test platform, the main use of uvm validation methodology, uart interface, systemverilog and uvm ic development and verification have a pre
uvm实战源码
- uvm实战教程源码，丰富的uvm demo testbench,可以学习uvm各个阶段的testbench搭建技巧，能学习到大量的uvm testbench搭建技能，比如factory和寄存器模型等重要机制，非常值得学习
AHB2-master
- AMBA AHB 2.0 VIP in SystemVerilog UVM
AHB5-master
- amba ahb2 协议vip，包括master和slave(AMBA AHB 2.0 VIP in SystemVerilog UVM)