搜索资源列表
memoryarray
- 由VHDL撰写的两记忆体转置程序，内含testbench与转置源码。-VHDL written by the two memory migration procedures, includes testbench and migration source.
des
- des解密加密的verilog源代码其中包含有测试源代码，仿真结果图-verilog des decrypt encrypted source code which includes testing the source code, Simulation results
TB_VHDL(adder)
- 加法器的VHDL源码及其对于的仿真Testbench 文件的编写-VHDL Code about adder for the "Simple Test Bench" example VHDL Code about adder for the "Simple Test Bench" example
counter
- 计数器的VHDL源码及其对于的仿真Testbench 文件的编写-VHDL Code about counter for the "Simple Test Bench" example VHDL Code about adder for the "Simple Test Bench" example
Text-IO
- 基于VHDL的Testbench读取文件的编写，很有用的 基于VHDL的Testbench读取文件的编写，很有用的-VHDL Code text_io for the "Simple Test Bench" example VHDL Code about text_io for the "Simple Test Bench" example
inputoutput_textio
- 关于VHDL读取文件的testbench编写的ppt介绍，挺有用的-testbench for text_io,it is very useful,isn t it.testbench for text_io,it is very useful,isn t it.
arm9verilog
- AMBA AHB verilog Source code
elevator_controller
- vhdl elevator controller with testbench
test
- 从文件中读取波形文件的testbench例子，大家可以参考-Read from the file testbench waveform file example, we can refer to
QAM16MapandDemapping
- 包含QAM16的调制与解调的整个工程，并且还有Testbench-Contains QAM16 of modulation and demodulation of the entire project
AD7924
- Core to read all channels from AD7924 with an external strobe. A testbench is available.
RAM
- 单端口RAM，自己写的单端口RAM，同步写入同步读出，包括TESTBENCH和测试模拟文件-RAM
Lab01
- 快速熟悉ISE软件的使用，适合初学者，是一系列小操作流程的集合。-To become familiar with using Xilinx ISE to draw schematic representations of PLD circuits To become familiar with using Xilinx ISE to conduct graphical waveform simulations of PLD circuits To become familiar with
Verilog_testbench
- 介绍在FPGA广泛使用的Verilog语言以及如何编写高效的testbench，让仿真更加接近实际模型。-Introduction widely used in FPGA Verilog language and how to write effective testbench, so that a more realistic simulation model.
32bitcarrylookaheadadder
- 32位超前进位加法器的源代码和testbench-32 bit carry look ahead adder and its testbench
seg7_disp_test
- seg7 display testbench
code
- 一个基于fpga的简单的实时心电检测系统，包括与pc通讯和qrs检测两部分-A simple fpga-based real-time ECG detection system, including communication with the pc and qrs detection of two parts
sr8b
- This a shift register of 8bit It includes testbench It works DE2-70 board-This is a shift register of 8bit It includes testbench It works DE2-70 board
Multiplier
- 使用三种不同结构（加法树、查找表、Booth算法）实现的乘法器，带有测试文件。-Use of three different structures (addition tree, look-up table, Booth algorithm) to achieve the multiplier, with testbench files.
Logicos
- Is a Simple andOr, xor, sr circuit on Verilog and his testBench