搜索资源列表
turbo[1].tar
- turbo码的verilog程序，有意者请下载。-turbo code verilog procedures Interested parties please download.
turbo-interleaver
- 基于FPGA的Turbo码交织器的设计与实现 比较实用
Turbo VHDL
- VHDL源程序
FPGA上实现TURBO码的编码
- 在赛灵思的FPGA上实现的TURBO码的编码程序
RSC.rar
- Turbo码编码器的两个分量编码器RSC，主要由四个移位寄存器和两个模2加法器组成,Turbo code encoder of the two component encoders RSC, mainly by the four shift register and the two-mode adder composed of 2
turbo
- turbo的VHDL代码 比较好啊 易后大家多多交流啊-Comparison of the VHDL code for turbo Well you lot of the easy exchange of ah
turbocodes_latest.tar
- turbo encode and decoder
turbodecoder
- 用vhdl实现turbo码的迭代解码，转某N人的程序-Using vhdl implementation of iterative decoding turbo codes, transfer of a person' s procedures for N
DSP_MATLAB
- 一、内容 含有《数字信号处理－理论、算法与实现》一书中所涉及到的绝大部分算法。 \Dsp_matlab 用MATLAB编写的信号处理程序，包含本书各个章节的 大部分例题。 二、运行环境 硬件环境：Pentium 200以上计算机，64M内存，真彩色显示卡。 软件环境：Windows 98/NT/2000，Turbo C，FORTRAN77 V5.10， MATLAB 5.X以上版本； -1, containing the
Turbo
- 基于fpga的交织编码器设计，主要讲叙如何在fpga上实现交织编码器。-something about turbo。
delete
- Turbo码编码器的删除模块，此模块是CCSDS标准系的码率为1/2和1/3的删除模块-Turbo code encoder to delete module, this module is the Department of CCSDS standard rate of 1/2 and 1/3 of the delete module
juanjiturbo
- 卷积编码和译码过程，维特比译码，含有测试程序-turbo encoder and decoder
EnergyEfficientVLSIArchitectureforLinearTurboEqua
- Energy efficient for turbo encoder decoder
IterativeDecodingofBinary
- In this paper, energy efficient VLSI architectures for linear turbo equalization are studied. Linear turbo equalizers exhibit dramatic bit error rate (BER) improvement over conventional equalizers by enabling a form of joint equalization and deco
MapAlgorithm
- However, turbo equalizers can be computationally complex and hence require significant power consumption. In this paper, we present an energy-efficient VLSI architecture for such linear turbo equalizers. Key architectural techniques include elimi
VerilogLangRefManual
- Simulation results show that energy savings in the range 30–60 and 10–60 are achieved in equalization and decoding, respectively. Furthermore, we present finite precision requirements of the linear turbo equalizer and an efficient rescaling metho
jiaozhiqi
- 是Turbo码交织器的VHDL设计与仿真的文献-Is the Turbo Code Interleaver Design and Simulation of VHDL literature
turbo
- Turbo仿真。VHDL语言。对学习编码很有帮助-Turbo
turbo
- Turbo code simulation. This code can be compiled on all platforms. The interleaver size is 10000. SNR can be varied according to user s need. However, each time SNR is changed, the code must be recompiled.-Turbo code simulation. This code
23984860-VLSI-Design-of-Turbo-Decoder-for-Integra
- In this paper, we propose a novel multi-code turbo decoder architecture for 4G wireless systems. To support various 4G standards, a configurable multi-mode MAP (maximum a posteriori) decoder is designed for both binary and duo-binary turbo co