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UART Transmitter. VHDL code and its testbench.
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simple uart vhdl behavioural model (package)
vhdl testbench example
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用VHDL编写实现的UART控制器源码，自带testbench，解压后用ISE打开工程文件即可。-Prepared with the VHDL source code to achieve the UART controller, bring their own testbench, after decompression project file can be opened with the ISE.
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文档详尽、已验证的UART工程，含有testbench文件。采用VHDL、Verilog语言编写。-Detailed documentation, has proven UART works with testbench file. Using VHDL, Verilog language.
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UART VHDL sources with FIFO-UART VHDL sources with FIFO,baudrate,receiver,transmitter,register,testbench
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