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USB 2.0 IP Core
- USB20的IP CORE,可以直接用在SOPC下，自动完成全部的枚举，只需修改枚举参数即可！-USB20 IP CORE, can be directly used in SOPC, automatically complete the enumeration. only a modification of enumerated parameters can be!
USB 1.1 IP-CORE和设计范例 VHDL源代码
- USB 1.1 IP-CORE和设计范例 VHDL源代码-Sample program for USB1.1 IP core design, VHDL source code
USB.rar
- 用VHDL实现的USB IP核，大家可以参考下,Use VHDL to achieve USB IP core, we can refer to the following
usb11.rar
- 基于verilog HDL的一个USB 1.1的IP 核，内有详细文档说明。,Verilog HDL based on a USB 1.1 of the IP core, which has detailed documentation.
vxwork_src.rar
- 大名鼎鼎的嵌入式操作系统vxworks的完整的源代码，支持多种体系结构的嵌入式处理器，如arm,x86,i960,mc68k,mips,ppc,sparc等，包含完整的实时多任务处理及网络tcpip,dhcp,rip等协议，tffs文件系统，以及各种硬件驱动程序如usb,-All the source code of Famous vxwork Embedded operating system , it supports the Embedded processor of many kinds
USB_Verilog_IP
- USB IP核VHDL源码(使用VHDL实现的USB IP core)-USB IP core VHDL source
usb_funct[1].tar
- usb2.0的IP核，可在QuartusII或MaxPlusII环境下实现编译和生成ip核-usb2.0 IP nuclear, QuartusII or the environment under MaxPlusII compile and generate nuclear ip
can
- 基于Verilog HDL 的一个CAN总线IP核。-Based on Verilog HDL a CAN bus IP core.
1
- 15个免费的IP核 usb11,i2c,pci_core,video_compression_systems等等.-15 free IP core usb11, i2c, pci_core, video_compression_systems and so on.
vivi-cs8900-yuxiaohui002.tar
- 支持CS8900网卡驱动，支持tftp传输的，vivi，主机ip地址默认设置为192.168.1.100,vivi默认设置地址为192.168.1.15，可以使用tftp进行传输-Support for CS8900 NIC driver, support tftp transfer, vivi, host ip address default to 192.168.1.100, vivi default address of 192.168.1.15, you can use tftp to
usb_latest.tar
- 用VHDL语言编写的USB 2.0IP核。USB 2.0的传输速率是高速率480 Mb/s，需要再外扩一个PHY。-This is a USB 2.0 compliant core，USB 2.0 allows data transfers of 480 Mb/s. Because of the high interface speed, an external PHY will be required with this core.
Usb_ISP1362
- 飞利浦公司Usb芯片ISP1362在nios中的IP核，可以用-Philips Usb-chip ISP1362 in nios in the IP core, you can use
usb20_ipcore_usb_funct
- usb 2.0协议的ip核，可用，里面程序有文档说明-usb 2.0 protocol ip core, can be used, which procedures are documented
usb
- USB完整代码 包括vhdl和verilog两种-usb ip core
mjpeg_3
- 基于usb摄像头的嵌入式视频监视中的pc端的视频接收与处理程序。通过输入arm开发板的ip就能获取及显示摄像头（Zc0103）的视频图像。-Usb based video surveillance camera embedded in the pc end of the video receiving and processing procedures. Arm development board by entering the ip camera will be able to access
verilog-usb--protel-design
- 基于FPGA的usb2.0 ip核设计，所用的语言是verilog-FPGA-based usb2.0 ip core design, the language used is the verilog
linux_transplantation
- 《S3C44B0开发板移植内核2.6 uclinux记录》以及一篇论文《基于Linux的USB 2.0 OTG IP核主机驱动的研究与实现》。-" S3C44B0 development board transplantation kernel 2.6 uclinux record" and a paper " Linux-based USB 2.0 OTG IP core host-driven research and implementation."
NVR_Client(V6.65)
- The iVMS-4000(V2.0) is the client application specially developed for the embedded DVR/DVS. It is applicable to DVR, hybrid DVR, NVR, DVS, IP Camera, IP Dome, audio/video decoder, and iVMS-2000 client software as well. The iVMS-4000(V2.0) client prov
usb
- USB的verilog IP模块，经过DesignCompiler综合验证-USB-verilog IP module, comprehensive verification through DesignCompiler
FPGA IP cores
- FPGA IP cores on verilog for USB CY7C68013, VGA, Ethernet DM9000A, Sound WM8731.