搜索资源列表
rs_decoder_31_19_6.tar
- Hard-decision decoding scheme Codeword length (n) : 31 symbols. Message length (k) : 19 symbols. Error correction capability (t) : 6 symbols One symbol represents 5 bit. Uses GF(2^5) with primitive polynomial p(x) = X^5 X^2 + 1
picoblaze07.3.20
- verilog HDL picoblaze07.3.20
fdivision
- 使用Verilog语言实现20分频的代码，简单易懂，经过medolsim仿真，可正确输出预期的波形，实现20分频。-Using the Verilog language to achieve 20 points frequency code, easy to understand, after medolsim simulation, correctly anticipated the output waveform frequency to achieve 20 points.
verilog_instance
- 20多个十分实用的verilog例子，如状态机，除法器等-More than 20 very practical verilog examples, such as state machines, divider, etc.
4945579081DCT_2D
- dct-20 verilog vhdl de2
cla20_n
- Verilog 20 bit的累加器 采用流水香设计，用5级4bit的超前进位加法器-Verilog 20 bit accumulator using water in Hong design, with five 4bit the look-ahead adder
20-SPI
- 采用EPM1278CPLD，通过verilog语言实现SPI接口的通信-By EPM1278CPLD, through the SPI interface verilog language communication
waveform_-generator
- 简易信号波形发生器，可以产生四种波形，频率1k-20K步进可调。学习Verilog HDL的好例子。-imple signal waveform generator, can produce four waveform, frequency 1 k-20 k step can be adjusted. Learning Verilog good example of HDL.
20frequency-divider
- 20分频器的实现，利用Verilog语言-realize 20 frequence device by Verilog
digit_deletion_game-rev1.0
- digit deletion game to be implented by verilog. This game was used in casio game before 20 years. I made it in verilog. Game rule is simple. number is generated in random and user will delete number in display out of order. Have Fun.
HIT_test
- 哈工大的组成原理课程设计，主要是verilog实现20几个常用指令-HIT the composition principles of curriculum design, verilog achieve 20 several commonly used instructions
ex
- 自己写的一个程序 verilog 电子设计大赛20-Himself wrote a program Verilog Electronic Design Contest 2011
WorkOneBetaC
- 低频数字相位测量仪 Verilog源代码 经过实测可用 信号频率20Hz-20KHz，步进20Hz 幅值0-5V，步进40mV。-Verilog code Through the measured signal frequency available 20 hz- 20 KHZ, step 20 hz Amplitude 0 to 5 v, stepping 40 mv.
EXAMPLES-ON-SYSTEM-VERILOG.tar
- THIS FILE CONTAINS AROUND 20 USEFUL EXAMPLES ON SYSTEM VERILOG (MEMORY-ARRAYS,LOGICS,DATATYPES ETC.)-THIS FILE CONTAINS AROUND 20 USEFUL EXAMPLES ON SYSTEM VERILOG (MEMORY-ARRAYS,LOGICS,DATATYPES ETC.)
CLA_20
- 用verilog语言编写的CLA_20文件。CLA_20是20位超前进位加法器的源代码，该代码验证后功能正确，读者可以自行编写testbench代码进行验证。-With verilog language CLA 20 files. CLA 20 is 20 lookahead adder source code after the code verification function correctly, readers can write their own testbench code fo
Experiment
- 经典入门verilog入门程序20个，从流水灯到液晶显示包括VGA驱动 入门必备精品-Classic entry Verilog entry procedures 20
Verilog HDL使用中该注意的问题及一些模块代码
- cpu仿真，提供vivado上的cpu仿真生成文件(cpu simulated,but no one can get 20 words in this short file how can I do? just tell you the simulated file and vivado system is 2015)
NEW
- Verilog投币式手机充电仪 清华大学数字电子技术基础课程EDA大作业。刚上电数码管全灭，按开始键后，数码管显示全为0。输入一定数额，数码管显示该数额的两倍对应的时间，按确认后开始倒计时。输入数额最多为20。若10秒没有按键，数码管全灭。(Verilog coin operated cell phone charger EDA major homework of digital electronic technology foundation course, Tsinghua Un
现有16位寄存器。初始值为0
- 现有16位寄存器。初始值为0。每个时钟周期寄存器的值会左移1位，并且将输入的数据data_in作为寄存器的最低位，寄存器原来的最高位将被丢弃。要求每个周期实时输出该16位寄存器对7求余的余数data_out[20]。(Existing 16 bit register. The initial value is 0. The value of each clock cycle register will shift 1 bit to the left, and the input data wil
serdes verilog 仿真模型
- serdes verilog 仿真模型 20位输入输出