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THS5651是一款高速DA转换器
- THS5651是一款高速DA转换器，最高转换频率可到达100MBPS，该程序利用VHDL语言对THS5651进行控制,THS5651 is a high-speed DA converter, the maximum conversion frequency can be arrived at 100MBPS, the use of VHDL language in the process control of the THS5651
FIRde-verilog-shixian
- 有符号DA算法的FIR滤波器的Verilog实现-A symbol of the algorithm of DA FIR filters Verilog realized
DA
- FPGA控制DAC2807的源文件，Verilog。附有简单文档-FPGA control DAC2807 source, Verilog. A simple document
ad_da_ctr
- 基于FPGA的ad和da转换Verilog代码，FPGA采用ep2c5芯片，做成异步fifo，ad芯片采用TI的ths1230,da芯片采用TI的TLV5619，仿真结果基本正确。-FPGA-based ad and da conversion Verilog code, FPGA using ep2c5 chip, made ??of asynchronous fifo, ad-chip using TI s ths1230, da chip uses TI s TLV5619, simula
tlc5615
- TLC5615串行DA的驱动接口,采用verilog编程-TLC5615 driver DA serial interface using verilog programming
DAC8812
- DA转换，Verilog HDL 编的，可实现DA转化。DA芯片用的是DAC8812，实现16位数模转化。-DA conversion, Verilog HDL code, the DA conversion can be achieved. DA-chip using a DAC8812, 16-bit analog-to achieve transformation.
AD_DA
- 非常好的,能够实现ad-da转换的子程序-Very good, to realize ad-da conversion subroutine
16_FIR
- 16阶FIR滤波器--本设计用VERILOG HDL语言串行DA算法实现16阶有限频率响应滤波器！-16-order FIR filter- this design language VERILOG HDL serial DA algorithm limited frequency response of 16-order filter!
high_speed_tap8_DDS
- 用verilog编写的高速8路并行dds模块，用于与高速da(1ghz或以上)接口产生任意频率正弦波，模块已经经过工程验证，用于产品中。-Verilog prepared with high-speed 8-way parallel dds modules for use with high-speed da (1ghz or above) interface have any frequency sine wave, the module has been proof for the prod
verilog.DA.FIR..
- 用verilog写的16阶串行DA算法FIR滤波器-Verilog written by 16-order FIR filter serial DA algorithm
test_in
- 用Verilog编写的产生图像的程序，实现24位数据量产生图像使用DA转换后直接显示-Verilog prepared using the procedure for selecting the images to achieve 24-bit image data generated using the DA converter and directly show the
dac121
- 采用verilog编写的高速串型DA芯片dac121驱动代码，占用le较少，效率高，目前我应用在较多产品上-Verilog prepared using high-speed string-type DA-chip dac121 driver code, occupation le small, high efficiency, the current I applied to more products
dds_final
- 使用Verilog HDL语言实现的一个DDS，可以发生0-10Mhz正弦波、方波、三角波，频率步进可调，FM调制、AM调制，调制度可调。DA芯片为8位并行，160MHz-Using the Verilog HDL language implementation of a DDS, can occur 0-10Mhz sine, square, triangle wave, frequency step tunable, FM modulation, AM modulation, adjusta
DA
- 采用Verilog在FPGA上实现一阶Σ-Δ DAC，仿真和实际验证都正确，基本可以达到16位DAC的信噪比
dac
- DA芯片输出控制 SPI协议 只写不读 FPGA用 verilog-DA-chip SPI protocol output control does not read write-only FPGA with verilog
DA
- Verilog HDL 写的１２位串口ＤＡ转换程序-Written in Verilog HDL conversion process 12-bit serial DA
Verilog-hdlFPGA
- 关于FPGA的提高篇，Verilog HDL语言写的， 包含LCD控制VHDL程序与仿真，AD/DA，MASK，FSK，PSK，正弦波发生器，等等经典程序-Articles on improving the FPGA, Verilog HDL language, and includes LCD control procedures and VHDL simulation, AD/DA, MASK, FSK, PSK, sine wave generator, and so the classi
DA_FIR_VERILOG
- 基于DA算法的FIR滤波器的verilog实现-DA-based FIR filter algorithm to achieve the verilog
my6
- fpga verilog程序，实现诸多模块功能，包括，数码管显示，与ad，da通信，与mcu通信，以便通过mcu将高速ad值显示在lcd显示器上。-fpga verilog program to achieve a number of modules, including, digital display, with the ad, da communication, communication with mcu, mcu high-speed through the ad to the val
da--sine
- 利用dds方法，通过DA输出正弦波，频率1KHz 频率根据代码可调-DA output sine wave frequency 1KHz (Verilog)