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verilogpll
- 用verilog语言编写的全数字锁相环的源代码,基于fpga平台-using Verilog language prepared by the DPLL the source code, they simply based on the platform
dpll
- dpll的verilog代码，完成数字锁相。用于时钟对准，位同步。-dpll the verilog code to complete the digital phase-locked. Alignment for the clock, bit synchronization.
dpll
- 基于Verilog的数字锁相环。包括三个模块，数字鉴相器DPD、数字环路滤波器DLF、数控振荡器 DCO三部分构成-Verilog-based digital PLL. Consists of three modules, the digital phase detector DPD, digital loop filter DLF, digitally controlled oscillator DCO three parts
DPLL
- 全数字锁相环的verilog设计，已通过仿真验证能迅速锁定相位-Digital phase loop lock design with verilog
FdplllzipP
- ＦＰＧＡ实现全数字锁相环，运用硬件描述评议议verilog HDL，顶层文件ＤＰＬＬ．Ｖ -FPGA implementation of DPLL, the use of hardware descr iption council meeting Verilog HDL top-level file DPLL is. V
verilog
- 全数字锁相环的verilog源代码，用于FPGA开发全数字锁相环-DPLL verilog source code for FPGA development DPLL
verilog-pll
- 用verilog写的倍频电路 文件中介绍DP-The multiplier circuit file by verilog introduced DPLL
dpll
- 用verilog编写的全数字锁相环，包括鉴相器，模K计数器，加减脉冲模块和分频模块，都经过验证-verilog based digital phase lock loop design, including phase detector,mode K counter, increment/decrement counter and frequency divider
dpll
- 数字锁相环 dpll的 编译通过,使用verilog HDL语言对锁相环进行基于FPGA的全数字系统设计,以及对其性能进行分析和计算机仿真的具体方法-Digital phase-locked loop dpll compiler through the use of verilog HDL language on the phase-locked loop FPGA-based digital system design, as well as its performance analysis