搜索资源列表
FPGA_Project_Files
- 基于sdram的pci设计,包含整个工程,verilog编写-The design is base on sdram, contain a whole project ,using the verilog language.
Verilog_module
- micron 1G内存条verilog模型,对应具体信号为MT8HTF12864HZ-800,内存颗粒为MT47H128M8CF-25-micron 1G DDR2 SDRAM verilog module
tut_DE2_sdram_verilog
- DE2 sdram 的verilog 教学材料-tut_DE2 sdram verilog.
memory-controller
- 存储控制器,包括CPUside,接口,MEMORY side三个部分,使用verilog语言-This represents the "memory controller" It runs with the assumption that it is being connected to PC100 SDRAM.
FSM
- FPGA学习资料,新手入门资料,VERILOG- Micron SDRAM DDR2 Simulation model Verilog
altera_sdram
- 基于quartus平台的sdram控制器设计(verilog 源码)-Based on the the quartus platform, the SDRAM controller design (Verilog source code)
Sdram_Control_4Port
- 使用verilog HDL写的sdram(SDR)的控制器源代码,具有很好的可移植性,试验的例子已经通过QuartusII 9.0编译通过,可以运行在cycloneII上-Controller source code using verilog HDL written in the sdram (SDR), has good portability, test examples via the QuartusII 9.0 compiler, you can run in cycloneII
Design-Of-DDR-SDRAM-Using-Verilog-HDL
- implementation of ddrsdram
sdram_mdl
- SDRAM的FPGA 工程。用Verilog编写。器件型号为K4S641632,经过实验板验证,绝对可用。-SDRAM FPGA project. Written in Verilog. Device model K4S641632, after the experimental board, absolutely available.
sdram_mdl
- FPGA控制SDRAM的工程,是用Verilog写的,很好用-FPGA to control the SDRAM project is written in Verilog, easy to use
sdram_me
- 用verilog代码控制sdram,sdram_module是顶层模块。控制8M x 16bits x4Banks sdram. -use verilog program to control the sdram
DE2_70_NIOS_10_flash
- 首先将此Verilog程序下载到DE2-70开发板上后,然后用NiosII软件将任何文件的二进制数据写入到ssram或者sdram等存储器重去,并可以指定起始地址。-First program this Verilog downloaded to the DE2-70 development board, and then the use NiosII software binary data of any file written to memory such as ssram or sdra
LL
- verilog语言描述的SDRAM程序代码。-verilog language to describe the the SDRAM procedure code.
sdram_mdl
- 用Verilog HDL编写的SDRAM控制程序,在DE2-70上测试通过,有很大的参考价值。-SDRAM control program written using Verilog HDL DE2-70 test passes, great reference value.
sdram_mdl
- SDRAM VERILOG源代码 控制读写-SDRAM VERILOG source code control read and write
Altera-SDRAM_controller-IP-CORE
- ALTRA官方提供的SDRAM的控制内核,VHDL和VERILOG版本都有,希望对大家有用-The ALTRA official SDRAM control kernel, VHDL and VERILOG version have the hope that useful
my_test_rw_pack9
- 基于Verilog HDL的SDRAM控制器。 实验条件: 工具:Quartus II 6.0 ,SignalTap II FPGA:Altera Cyclone EP1C12Q240C8N SDRAM:HY57V283220T-6-SDRAM controller based on Verilog HDL. Experimental conditions: Tools: Quartus II 6.0, SignalTap II FPGA: Altera Cyclon
SDR-SDRAMverilog
- 经典三星SDR SDRAM读写verilog代码分享-Classic Samsung SDR SDRAM read and write verilog code share
Sdram_Control_4Port
- SDRAM控制器的verilog源代码实现-SDRAM controller Verilog source code to achieve
Sdram_PLL
- SDRAM的锁存器控制程序verilog代码-The SDRAM latches control program verilog code