搜索资源列表
drv_dm900
- 这是去年我编写的基于xilinx FPGA的MAC IP 核开发的驱动DM9000的源代码。基于Verilog 语言。-This is the last year I wrote based on xilinx FPGA the MAC IP core developed DM9000 driver source code. Based Verilog language.
vivado_LED_Flow
- 本例程使用vivado2014.4工具，利用xilinx Basys3 实验板实现板载流水灯的两种模式控制。-This project uses verilog HDL to realize the the control of 16 leds loaded on Xilinx Basys3 board.
SegSimplified
- 本工程使用verilog HDL和vivado2014集成开发环境实现利用xilinx Basys3开发板上4位数码管显示从0到9999的计数器功能。-This project uses verilog HDL to realise counting 0 to 9999 on the 7-seg LED loaded on Xilinx Basys3 board.
ethernet
- 在xilinx用verilog实现工业以太网的全部文件-industrial ethernet in xilinx
I2C_Controller
- 这是个人设计的I2C总线的控制器。已封装好I2C总线的4种基本操作（写单字节，写多字节，读单字节和读读多字节）。在这个资源当中，包含自己写的设计文档和使用方式，以及Verilog源代码。此过程经过Xilinx开发板下载验证且没有问题。-This is the controller of the personal project I2C bus. I2C bus has a good package of four basic operations (to write a single byte,
DDR3_128M16bit_2Port64bit
- Xilinx spartan6 DDR3驱动，编程语言Verilog，基于MCB硬核。-Xilinx spartan6 DDR3 driver based on MCB ip core,coding by verilog.
Use-lab2-ISE-software
- 熟悉掌握VerilogHDL语言并能用其建立基本 的逻辑部件在Xilinx ISE平台进行输入、编辑、 调试、仿真-Familiar with Verilog HDL language and be able to establish its basic logical components in Xilinx ISE platform for input, editing, debugging, simulation
udpip
- 赛灵思XILINX FPGA verilog写的UDP/IP协议，可用。-I am prepared to use verilog UDP protocol, the test is available.
snake
- 自己写的verilog贪吃蛇程序，使用vivado2015.2软件编写综合的，硬件平台是xilinx的basys3平台，当检测到碰撞时，led灯会亮起-Write your own verilog Snake program, using the software to prepare a comprehensive vivado2015.2, the hardware platform is the basys3 xilinx platform, when a collision is det
axi_jesd204b
- ADI JESD204接口的ADC与Xilinx FPGA接口IP，包含Verilog和VHDL源代码，AXI总线接口，ADC串行控制接口-ADI IP for interfacing JESD204 ADC to Xilinx FPGA, include Verilog/VHDL source code, AXI interface and serial config interface
wiznet5500_Verilog
- 使用Xilinx Spartan-6 XC6SLX9的FPGA驱动Wiznet5500网卡芯片的Verilog设计，可以发送和接收，已经测试，无误。-Using the Xilinx Spartan-6 XC6SLX9 FPGA driver The Wiznet5500 network card chip Verilog design can be sent and received, has been tested, and is correct.
Implement-a-CPU
- 在FPGA赛灵思基础3上使用Verilog HDL实现支持MIPS操作子集的CPU-Implement a CPU which supports a subset of MIPS operations using Verilog HDL on FPGA Xilinx Basys 3
spi_flash_controler
- w25q64 spi flash verilog code .use xilinx ise .
idwt
- Time Resolution for simulation is 1ps. Waiting for 1 sub-compilation(s) to finish... Compiled 4 Verilog Units Built simulation executable G:/Techscope/On going Mtech/Miniproject/1DDWT/xilinx/top_dwt_isim_beh.exe Fuse Memory Usage: 101756 KB Fuse
04_led_test
- verilog 入门 流水灯verilog 入门 verilog 入门 verilog 入门(verilog led test xilinx)
07_uart_test
- fpga 串口 Verilog 黑金的板子，入门(fpga uart test xilinx)
uart
- UART的串口程序，收发功能都已实现，直接可用(UART serial procedures, transceiver functions have been achieved, directly available)
VGA
- vga code for fpga 3s500e spartan xilinx code verilog tutorial video graphics array in verilog interfacing with fpga xilins spattan 3e very easy to learn
sequence detector
- sequence detector in verilog for xilinx
FIR
- FIR filter in verilog for xilinx ise design suit