搜索资源列表
mac控制器
- mac控制器ip核，语言verilog,开发环境xilinx ise,quartus ii等
xapp514_aes3-audio
- DVB数字音频接口(AESEBU)encoder源码,包括VHDL和VERILOG,基于XILINX FPGA,已验证.-AES-EBU interface,VHDL,VERILOG
led
- 基于xilinx spartan6 的verilog 代码实现nexys6的流水灯程序-floop leds display on nexys3 xilinx spartan6
all
- 基于FPGA的频率测试器的verilog HDL代码，测试范围1-10MHz，用XILINX公司的ISE软件打开。-Based on FPGA-frequency test the Verilog HDL code, test range 1-10MHz, with XILINX ISE software to open.
verilogcode
- 这是用于xilinx virtex-2 pro产品的误码仪方案verilog HDL代码-verilog code for bit-error rate tester
Ballastic_Calculator
- Ballastic Calculator Interface designe for Army TANK (Xilinx Verilog, Schematics)
dds_easy
- 直接频率合成DDS模块的ise工程，可以直接下载，在Spartan3/Spartan3E上验证通过。该DDS模块可以产生双通道的不同频率的正弦波，也可以产生同频的任意相位差的相移波形。本模块累加器位数为32位，可以产生12位相位精度12位量化精度的正弦波。该设计例化一个Block Ram，为节省储存空间仅需要储存1/4周期的数据。根据需要，可以重新修改数据，改变波形。-DDS direct frequency synthesizer module ，ise project, can be dir
freq_meter
- Frequency meter Verilog implementation for Xilinx XC2C256. MT10T7 7-seg LCD used for output.
VerilogProject
- 开发环境为Xilinx的Ise,都是一些经典的Verilog工程实例，对初学者有一定借鉴意义！-verilog project under ise environment
verilog_ps2_lcd
- 一个XILINX器件用Verilog实现在LCD上显示从PS口按键输入的字符的代码。-LCD display and ps key input
I2C_ise9migration
- IIC 的Verilog实现，工程是在Xilinx的ISE9.1上实现的-IIC of the Verilog implementation project was implemented on Xilinx' s ISE9.1
ALUC
- 用verilog语言中xilinx平台上实现single ALU,包括alu的基本MIPS指令运算,ALU control的实现-Xilinx verilog languages with the platform to achieve single ALU, including the basic MIPS instructions alu operations, ALU control implementation
ddr2_sdram
- xilinx spartan2 fpgaddr2控制代码，使用verilog编写，可综合-xilinx spartan2 fpgaddr2 control code, using verilog preparation, can be integrated
XILINXSPARTAN_3Everilog2
- XILINX 的SPARTAN_3E 控制液晶显示屏显示字符串的verilog程序-XILINX 的SPARTAN_3E verilog FPGA use Verilog HDL to display a char on the lcd module lcd_control( input clk,
comp4
- 用verilog编了一个比较器，开发环境是xilinx ise10.1-Verilog compiled using a comparator, the development environment is the xilinx ise10.1
adder4
- 这是一个用verilog编写的四位加法器，编程环境是xilinx ise10.1.-This is a written with the four adder verilog, programming environment is xilinx ise10.1.
gate
- 用verilog编写，与或非门的演示程序，编程环境是xilinx ise10.1.-Prepared using verilog, or non-doors demo program with the programming environment is the xilinx ise10.1.
alu4bitsynthesizable
- its a 4 bit arithmetic nd logical unit code in verilog. the software which is used for it is xilinx
Chipscope_example
- A easy simple for Xilinx Chipscope Pro, the example shows how to insert cores of VIO, ILA from core generator and verilog code.
serial_communication
- 使用Xilinx公司的FPGA，采用Verilog HDL语言实现串口数据的发送与接收。-Using Xilinx' s FPGA, Verilog HDL language used to send and receive serial data.