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clock_time
- 本文件解压后clock_time.vhd采用编程环境maxplusII，完成时间秒定时、记时，设置时间秒、声光报警等功能。-this document unpacked clock_time.vhd maxplusII use programming environment, the time for completion seconds timing, Hutchison, the set-up time seconds, sound, light, alarm functions.
数据选择器vhd源代码
- 数据选择器，半加器，3-8译码器vhd源代码。是最近学校的实验内容。我要成会员，所以都发上来供大家参考。-data selection, half-adder ,3-8 decoder vhd source code. Recent experimental schools content. I want to become members and therefore has made onto for reference.
[eda]vhdl
- 福州大学EDA选修课所有实验课程代码。VHDL语言描述（vhd），以及电路图（gdf）-Fuzhou University EDA optional courses in all experimental code. VHDL descr iption (vhd), and circuit (GdF)
2Dfft
- VHDL 关于2DFFT设计程序 u scinode1 ∼ scinode9.vhd: Every SCI node RTL vhdl code. The details can be seen in the following section. u 2dfft.vhd: The top module includes these scinodes and form a 3x3 SCI Torus network, and it support these sub-mo
yibutongxin
- 本程序是用VHDL语言实现异步通信控制器， hao1.vhd为主程序，hao1.scf为仿真波形-this procedure is used VHDL asynchronous communication controller, mainly hao1.vhd procedures, hao1.scf for simulation waveforms
vhd
- 基于maxplusII的EDA设计，自动绕线机的设计源程序。-maxplusII Based on the EDA design, automatic winding machine design source.
zldjkzjq
- max+plusII下编成的直流电机控制器vhd-under monument of the DC motor controller vhd
jcq
- max+plusII下的各种功能的计数器vhd-under the various functions of the counter vhd
DaFilter
- /* This program generates the DApkg.vhd file that is used to define * the DA filter core and gives its parameters and the contents of the * Distributed Arithmetic Look-up-table \"DALUT\" according to the DA algorithm-/ * This program generate
pinluji.rar
- 四位十进制频率计设计 包含测频控制器（TESTCTL），4位锁存器(REG4B)，十进制计数器（CNT10）的原程序(vhd)，波形文件(wmf ),包装后的元件(bsf)。顶层原理图文件（Block1.bdf）和波形。 ,Four decimal frequency meter measuring frequency controller design includes (TESTCTL), 4 bit latch (REG4B), decimal counter (CNT10) of t
vhd-util-code.rar
- xen source 推出最新的VHD操作工具VHD-UTIL 实现源码,超强，学习高手的设计思路,source code about VHD-UTIL
13
- para13： fifo.vhd FIFO（双口RAM） fifo1.vhd FIFO（嵌入式EAB） fifo2.vhd FIFO（LPM）-para13: fifo.vhd FIFO (dual port RAM) fifo1.vhd FIFO (embedded EAB) fifo2.vhd FIFO (LPM)
uart.vhd
- this modul is serial send & resive for RS232
fifo.vhd
- This a FIFO in VHDL Code-This is a FIFO in VHDL Code
myAD558
- AD558 VHDL 程序 *.vhd 包括各种波形发生，正弦波，三角波，梯形波-AD558 vhdl program*.vhd
lift.vhd
- 用VHDL实现了电梯的模拟程序，实现了自动判断楼层，然后根据客户需求和楼层最近原则，实现自动判断上下行，还有报警，强制开门等功能-Achieved using VHDL elevator simulation program, to determine the realization of an automatic floor, and then based on the principle of demand and the floor recently, automatically dete
vhd
- 波形发生器 是基于VHDL的原码；可以下载下来看看。-waveform generator for VHdl
vhdl-digital
- VHD L数字钟 设计源码 包括 设计思想 设计模块 -VHD L source, including digital clock design design design module
Circuit-Design-With-VHD
- Circuit Design With VHD
uart-to-GPIO.vhd
- -- Filename ﹕ uart.vhd -- Author ﹕ZRtech -- Descr iption ﹕串口接收与发送程序 -- 本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证-- 程序的功能。程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控制器，10个bit是1位起始位-- 8个数据位，1个结束位。串口的波特律由程序中定义的div_par参数决定，更改该参数可以实现相应的波-- 特率。程序当前设定的div_