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8倍频vhdl
- 该文件可用vhdl语言实现时钟8倍频，运行环境可在maxplus2和ise的仿真软件上-the document available VHDL Language 8 clock frequency, the operating environment and ideally maxplus2 simulation software
beipin_4
- 自己编写的vhdl语言来实现的四倍频电路，自我感觉还可以，也通过了编译，如果有需要就下载去看看吧-prepared vhdl own language to achieve the four frequency circuit, a sense of self, can also, through a compiler, If there is a need to look at the downloaded Look here
3_Freq
- 3倍频实用稳定算法的VHDL实现（XILINX CPLD）
EP2C20_TEST.rar
- 内含无刷电机驱动VHDL模块，读码盘4倍频模块，并用NIOS核实现简单无刷电机闭环控制。,Brushless motor driver includes VHDL modules, reading frequency module plate 4, and nuclear NIOS simple closed-loop control of brushless motor.
twice_freqencey
- 用Verilog直接完成倍频的算法,经过了quartus8.0的时序仿真-Verilog multiplier used directly to complete the algorithm, as a result of timing simulation quartus8.0
count_plus_last
- 对电机的编码器输入的正交编码信号进行4倍频处理 ，生成一个新的计数脉冲 ，同时判断电机的转动方向，输出一个方向标志电平信号，从而可以让DSP知道电机的转速和方向。-On the motor encoder inputs of the quadrature encoder signals 4 octave treatment, generates a new pulse count and at the same time to determine the direction of motor r
DCM
- ISE实现DCM组建例化，得到3倍频时钟-ISE to achieve established cases of DCM, received 3 octave clock
dds
- 基于FPGA的DDS设计，本程序采用verilog HDL语言编写，使用DDS+Pll倍频-The DDS-based FPGA design, the procedures used verilog HDL language, the use of DDS+ Pll frequency
Fredevider_n
- 任意N偶数倍频率分频器VHDL语言，编译器MAX_PLUS2-Any even multiple of the frequency divider N VHDL language, compiler MAX_PLUS2
twice_clk
- 对输入时钟进行2倍频 已在modelsim中通过仿真 建议进行后仿 应用上来看 是可以使用的-the function of the module is frequency multiplication，and the module had been test and verified by modelsim,so the products can be employed with 100 ease by each consumer.think you!!!!
CyclonePLL
- Cyclone™ FPGA具有锁相环（PLL）和全局时钟网络，提供完整的时钟管理方案。Cyclone PLL具有时钟倍频和分频、相位偏移、可编程占空比和外部时钟输出，进行系统级的时钟管理和偏移控制。Altera® Quartus® II软件无需任何外部器件，就可以启用Cyclone PLL和相关功能。本文将介绍如何设计和使用Cyclone PLL功能。 PLL常用于同步内部器件时钟和外部时钟，使内部工作的时钟频率比外部时钟更高，时钟延迟和时钟偏移最小，减小或调整时钟
3fp
- 奇数分频和倍频(只需修改参数就可以实现较难得基数分频和倍频)-Odd frequency and frequency-doubling (just modify the parameters can be achieved relatively rare sub-base frequency and octave)
beipin_test
- 实现任意倍数的倍频,帮助大家解决VHDL倍频问题,-The realization of arbitrary multiples of the octave, octave VHDL help people solve problems,
statemachine
- 基于状态图的光电编码器4倍频vhdl程序，输入相位差90度的两相，输出倍频和方向信号-Based on the state of the optical encoder Figure 4 multiplier vhdl procedure, enter a 90-degree phase difference of two-phase, frequency and direction of the output signal
pll
- 是quartus2的仿真倍频电路，用于产生倍频时钟！-Is a multiplier circuit simulation quartus
Freq_4
- 伺服电机编码器四倍频源程序，已经在工程中应用。非常有用。-it is important,it has been use in my project.i hope it is useful to everyone
BPQ
- 倍频器-WE
pll
- 利用qaurtus的内的ip核定制锁相环实现对信号的倍频-The use of the ip qaurtus approved system PLL multiplier on signal
chengxu
- 4位乘法器，4位除法器，K倍频的VHDL实现-Four multipliers, four dividers, K multiplier of VHDL
VHDL
- 基于VHDL的数字倍频器设计，这里只提供个算法，希望对你的编程有所启发。-Vhdl based on the number of times the frequency of the design,Here only to provide an algorithm, hope for your programming has been inspired.