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44vhdl
- 44个vhdl实例 注1: 含有不可综合语句,请自行修改 注2: 一些PLD只允许I/O口对外三态,不支持内部三态,使用时要注意 注3: 设计RAM的最好方法是利用器件厂家提供的软件自动生成RAM元件,并在VHDL程序中例化-44 VHDL examples Note 1 : Includes an integrated statement, the initiative to revise Note 2 : Some PLD only allows I / O exte
VHDL
- 注1: 含有不可综合语句,请自行修改 注2: 一些PLD只允许I/O口对外三态,不支持内部三态,使用时要注意 注3: 设计RAM的最好方法是利用器件厂家提供的软件自动生成RAM元件,并在VHDL程序中例化
serial
- VHDL实现串口控制逻辑源代码,包括各个模块的具体实现和元件例化-Serial control logic to achieve VHDL source code, including various modules and components to achieve the specific cases of
eda-chengxu
- VHDL语言源程序,使用元件例化的方法设计简易数字钟-VHDL language source code, the use of components instantiated designed simple digital clock
vhdl
- vhdl代码串口的实现,每个部分的代码别写好了,元件例化一下即可用,-my english is poor ,i hope this make you understand and help you this is Serial implementation vhdl Categories:hardware
fir
- 真正意思上的fir滤波器课程设计,基于quartus II9.0的vhdl代码。有原理图输入和例化元件-The real meaning of the fir filter design program, based on quartus II9.0 the vhdl code. A schematic of components and cases
Generic_NOR3_gate_design
- 设计一个带类属参数的或门,它有N 个输入,N 的默认值为3。在顶层元件中将该类属元件例化2 次。在一个元件中将类属参数改变为N=4,而在另在一个元件中改变为N=5。-The way of using generic in VHDL design is shown in the Ninput NOR gate.
counter100
- VHDL语言 FPGA 一百进制计数器 元件例化方法-VHDL, FPGA hundred cases of binary counter element method
VHDL-digital-clock-
- VHDL编写的数字钟,采用元件例化的方法,可实现调秒 调分 调时 报时 闹铃的功能 开发板使用的是EP3C16Q240C8-Digital clock written in VHDL, using the example of the way components can be adjusted to achieve sub-second tone when the alarm tone Times feature development board using EP3C16Q240C8
VHDLxiaochengxu
- 一些简单的VHDL小程序。 VHDL 小程序源代码: led七段译码 简单调用 秒表 元件例化-Some simple VHDL applet. Small VHDL source code: led seven segment decoding simple example of calling a stopwatch components
serial
- 用VHDL测试代码进行存储器读写测试,使用元件例化的方法-experiment of visiting SRAM using the means of components
VHDL_commponet
- fpga设计中利用vhdl语言的元件例化语句和程序包可以优化代码,附有加法器,触发器的程序实例-plus and the other devices
Flying-Adder
- Flying-Adder是一种新型全数字结构频率合成器,压缩包包含txt文本和说明作用的图片,文本是VHDL代码,代码分为不同模块,再用元件例化。-VHDL Code and Some Images for Flying-Adder Frequency Synthesizer. It s a All-digital Novel Structure.
component_timer_counter
- Quartus环境下基于VHDL元件例化的数字钟程序-Zhong Chengxu digital VHDL component instantiation based on Quartus environment
shuzizhong
- 数字钟,校时较分,显示,用元件例化写的vhdl文件,两个24进制,1个60进制计数器-Digital clock, when the school over the points, show cases with elements of writing vhdl file, two 24-band, a 60-ary counter
exp5
- 用 VHDL 语言设计一半加器电路,然后用元件例化(COMPONENT)语句调用两个半加器电路,用结构描述实现一个全加器。-Design using VHDL half-adder circuit, and then use component instantiation (COMPONENT) statement invokes two half adder circuit, with the structure described in the realization of a full a
Four-binary-adder
- 熟悉 VHDL 语言的模块化设计,了解元件例化和打包调用语句。用 VHDL 语言设计一半加器电路,然后用元件例化(COMPONENT)语句调用两个半加器电路,用结构描述实现一个全加器。-The modular design of VHDL language familiar to understand the components and packing cases call statement. Design using VHDL half-adder circuit, and then us
shuzizhong
- 基于VHDL语言的数字钟,有元件例化,修改时钟功能 Quartus II平台-VHDL language based digital clock, there are component instantiation, modify clock function Quartus II platform
quanjia
- 通过VHDL语言编写的一位全加器程序,该程序是经过元件例化的方式实现-VHDL language through a full adder program, which is the result of component instantiation way to achieve
3 8
- 用VHDL多种方法实现3-8译码器,元件例化(use VHDL realize 3-8decoder)