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STOPWATCH
- 是基于FPGA/CPLD的跑表程序，可以存储记录多个运动员的跑步时间，是利用VHDL语言编写的，可以有助于学习EDA技术，可以参考学习，可以帮助你完成VHDL语言的课程设计。-Is based on FPGA/CPLD s stopwatch program, many athletes can store records of running time, is the use of VHDL language, and can help to learn EDA, can refer to t
finaldesign_watch
- 基于VHDL的数字跑表源码，芯片采用ALTERA公司的ACEX1K 系列的EP1K10TC100-3，项目设计过程中，用EDA技术作开发手段，运用VHDL语言，实现从0.01秒到59分59秒59 的设计。-VHDL-based digital stopwatch source, ALTERA chip company ACEX1K series EP1K10TC100-3, the project design process, by means of EDA technology for th
practise
- FPGA实验板设计一个数字跑表。根据题目要求利用VHDL语言设计出一个系统，包括分频器，开关消抖，使能控制，计数器，锁存器，数据选择器及显示译码器。-FPGA experimental board design a digital stopwatch. According to subject the use of VHDL language to design a system, including the divider, switch debounce, enable control, c
VHDL_paobiao
- 用VHDL语言设计一个跑表，计时范围为59.99秒。-Write a time range using VHDL language to 59.99 seconds in the stopwatch
dig_watch
- fpga实验，基于VHDL语言的数字跑表设计，其中包含有存储模块。-Fpga experiment, the digital stopwatch designed based on VHDL language, which contains a storage module.