搜索资源列表
General-memory-VHDL-code-library
- 通用存储器VHDL代码库。fifo,ram寄存器的代码和测试模块。-General-purpose memory VHDL code base. fifo, ram register code and test modules.
fifo
- 用vhdl语言实现对八位数据进行缓存的控制-With VHDL language implementation to eight of the data cache of control
Flag-of-asynchronous-FIFO
- Quartus平台,VHDL代码编写的带标志位的异步FIFO。-Quartus platform, VHDL code is written with the sign bit of the asynchronous FIFO.
EDA-experiments-based-on-VHDL
- 上传的文件包括E有关EDA实验的程序,比如FIFO,秒表,数字钟,七段数码管,状态机检测序列-The files uploaded contain some source code of EDA experiments based on VHDL, such as FIFO, digital clock, stop watch, digital tubes and sequential detector.
fifo
- 基于VHDL语言的fpga 实现FIFO 源程序,经验证可用,开发环境Quartus -VHDL FPGA FIFO QUARTUS II
FIFO
- Quartus下VHDL编写的一个FIFO模块,调试于c6000系列。控制Cache输入输出数据-A FIFO module in VHDL Quartus, commissioning c6000 series
FIFO
- 基于vhdl语言的fifo设计,方便你了解先进先出理论-Based on the the vhdl language of fifo design, allowing you to understand the first-in, first-out theory
fifo
- 先进先出存储器的接口设计,采用VHDL语言-FIFO memory interface design, using VHDL language
FIFO
- FIFO在VHDL上的实现。没有注释,较为完善,已通过编译。-FIFO implementations in VHDL. No comment, more perfect, has compiled.
FIFO
- FIFO的资料,包括文档说明已经一个VHDL文件。-FIFO data, including document describes a VHDL file.
fifo
- FIFO的VHDL代码,最简单的同步FIFO设计,仅供参考-FIFO VHDL code
FPGA-FIFO-VHDL
- 这是一个基于FPGA的异步FIFO设计,利用的VHDL硬件描述语言,内容分析清楚,附带完整代码-This is an FPGA-based asynchronous FIFO design, the use of VHDL hardware descr iption language, content analysis, with complete code
Async-FIFO-VHDL
- 异步FIFO VHDL代码实现,包括:async_fifo_show_ahead.vhd, async_fifo_show_ahead_rd_task_logic.vhd,async_fifo_show_ahead_wr_task_logic.vhd, sync_r2w.vhd,sync_ram_std_dc.vhd,sync_w2r.vhd-The asynchronous FIFO VHDL code implementation, including: async_fi
vhdl-Language-routine-highlights
- 工程中常用的VHDL控制模块,包括三态门,SDRAM,FIFO,PLL,RAM,FIlter等模块,非常实用的工程代码-Control module of VHDL is commonly used in engineering, including the tri-state gate, SDRAM, FIFO, PLL, RAM, FIlter module, very practical engineering code
VHDL-memory
- 存储器的VHDL描述,包括ROM,RAM,FIFO,stack等多种类型-design of memory by VHDL
SLAVE-FIFO-8BITS
- EZUSB FX2 的 SLAVE FIFO例程,包含8051的Firmware以及FPGA的FIFO控制代码 -EZUSB FX2 SLAVE FIFO sample program, including the 8051 firmware, and 8-bit VHDL slave FIFO interface code for FPGA
fifo
- FIFO缓存器的设计及VHDL测试平台代码-FIFO buffer design and VHDL testbench code
Asynchronous-FIFO
- Asynchronous FIFO Implementation in VHDL
fifo
- 设计一个同步的双端口fifo ,大小为8*128。-Designing a synchronous dual-port 8* 128 fifo using VHDL.
FIFO
- 用VHDL语言实现一种异步FIFO,并做时序仿真和功能仿真检验正确性。-Achieve an asynchronous FIFO using VHDL language, and do functional simulation and timing simulation test accuracy.