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viterbidecoder
- 提供实现了（2，1，7）卷积码的维特比译码的源程序，采用了最大似然算法，介绍了软判决维特比译码算法过程的三个步骤：初始化、度量更新和回溯译码。-for achieving a (2,1,7) Convolutional Codes Viterbi decoding of the source, using the maximum - likelihood algorithm, introduced a soft-decision Viterbi decoding algorithm of the
ViterbiDecodeK9R12HardDecision
- viterbi 硬判决译码，基本实现了（2，1，9）卷积码的硬判决译码，用modelsim RTL仿真通过-hard-decision viterbi decoding, the basic realization of the (2,1,9) convolutional codes hard decision decoding, using modelsim RTL simulation through
viterbi
- This a code generator for some kinds of viterbi decoders. It can generate the synthesiable verilog HDL codes. These have been verified under simulation. The generator itself is released under GPL license but the Verilog HDL codes generated by it is w
viterbi
- 高效率的viterbi译码，对通信中的卷积码进行译码-Efficient viterbi decoding of communications for decoding convolutional codes
VD-vhdl-Code
- this codes are for convolution encoder and Viterbi decoder synthesis and implementation.
finial_test
- 卷积码和Viterbi译码的源程序，在Xilinx ISE环境下使用Verilog编写，有助于卷积码和Viterbi译码的学习-Convolutional codes and Viterbi decoding of the source, in the Xilinx ISE environment, use of Verilog prepared to help convolutional codes and Viterbi decoding of the study
Viterbi-verilog-codes
- viterbi的无线局域网802.11协议接收端重要的一步。该资料为viterbi的verilog代码，它占用的资源相对比较低，而性能又高。-the viterbi wireless LAN 802.11 receiving end the important step. The viterbi verilog code, it takes up resources is relatively low, and high performance.
gdi1
- Viterbi decoder is used for decoding data encoded using Convolution Forward Error Correction codes or data that suffers inter-symbol interference. They occur in a large proportion of digital transmission. Viterbi decoders employed in digital wire
verilog-juanjima
- 卷积码是一种重要的前向纠错信道编码方式，其纠错性能常常优于分组码，且(2,1,7)卷积码已应用于现代卫星通信系统中。Viterbi译码算法能最大限度地发挥卷积码的优异性能。这里采用Verilog HDL语言设计出(2,1,7)卷积码的编码器模块和基于Viterbi算法的译码器模块，译码器采用全并行结构，译码速度快-Convolutional code is an important forward error correction channel coding method, and