搜索资源列表
SKRETD(low_power)
- 硕士论文，viterbi译码器的低功耗设计，最后附带源码，VHDL-master's thesis, Viterbi Decoder low-power design, the final collateral source, VHDL
trelisstd
- vhdl coding for testing viterbi
viterbi_binary_hard_c
- vhdl code for viterbi decoder
VD-vhdl-Code
- this codes are for convolution encoder and Viterbi decoder synthesis and implementation.
finial_test
- 卷积码和Viterbi译码的源程序，在Xilinx ISE环境下使用Verilog编写，有助于卷积码和Viterbi译码的学习-Convolutional codes and Viterbi decoding of the source, in the Xilinx ISE environment, use of Verilog prepared to help convolutional codes and Viterbi decoding of the study
encoder
- 802.11a卷积码的实现，使用公式133和177，可以用标准viterbi解码-802.11a convolutional code to achieve, using the formula 133 and 177, you can use standard viterbi decoding
The-viterbi-algorithm-(1)
- Vetrbi decoder VHDL code
VTCSp04
- viterbi decoder VHDL material
rtl_viterbi_veeRen
- RTL design Viterbi decoder using VHDL