mips single cycle implementation five files auxiliary pc data memory instruction memory adder forwarding

使用verilog代码描述了一种简单的单周期MIPS处理器实现，并在ModelSim SE6.5c调试通过。-The verilog code describes a simple, single-cycle MIPS processor implementation, and debugging through in ModelSim SE6.5c,.

用logisim写的单周期CPU，可以跑MIPS汇编编译的二进制代码，测试完美通过，供学弟学妹参考，计算机组成原理试验-Logisim write cycle with a single CPU, you can run the MIPS assembler binary code, test perfect pass for mentees reference, computer composition principle test