verilog语言实现的基于MIPS体系结构的微处理器程序，一个时钟周期执行一条指令。,verilog language MIPS-based microprocessor architecture, an implementation of a clock cycle instructions.

simple clock over verilog

verilog 程序，用于通讯系统测试，输入40MHz时钟，40倍分频之后，输出1Mhz时钟-verilog procedures for communication system testing, 40MHz input clock frequency to 40 times, the output clock 1Mhz