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signal_cpu_sort
- Use the verilog language write a MIPS CPU code, and have additional instruction, for example: selection sort instruction. The code has contain combination circuit and sequenial circuit. CPU have contain ALU, ADD, ALU_CONTROL, DATA_MEMORY, INST_ME
embedded_risc
- 一个嵌入式RISC CPU 的Verilog 设计源码，可综合。内含详细的设计文挡。-an embedded RISC CPU design Verilog source code can be integrated. Detailed design containing the text block.
leg_source
- verilog hdl编写,六段流水线CPU.程序完整，功能强惊。分为多模块编写-verilog hdl prepared replace pipelined CPU. The integrity of the process, strong function scared. Divided into multiple modules prepared
cpu
- 精简指令cpu，用verilog编写，详细的教程
RISC_Core.ZIP
- 这是一篇关于8位RISC CPU设计的文章，其中包含了用Verilog语言编写的CPU内核程序
ethernet_verilog
- 这是一个很好的Verilog 编写的8位RISC CPU源码（可做为MCU），并且包括完整的C 语言的测试代码。-This is a very good preparation Verilog 8-bit RISC CPU source (available as MCU), and includes a complete C language test code.
BuildingPaPRISCPSystemPinPanPFPGA
- 一个32位 RISC CPU 核心，由Verilog 编写而成-A 32-bit RISC CPU core, written by Verilog
ARM-Verilog-HDL-IP-CORE
- ARM处理器的IP核，用verilog编写的，对处理器和相关的CPU架构知识有很大帮助。-ARM processor IP core, written in verilog processor and CPU architecture knowledge.
PipelineCPU
- 这是我们设计的一个MIPS流水线CPU，基于Verilog HDL语言实现。它与传统的MIPS流水线CPU不同点在于，5个流水段各自维护一个变量(SelType)表明当前正在执行的指令类型，这样处理数据冒险、loaduse冒险或者跳转冒险时候每个段都能知道其他段正在处理的语句，从而方便我们的处理。-This is a MIPS pipelined CPU based on Verilog HDL language to achieve. It the the MIPS pipelined CPU
OpenMIPS_VerilogHDL_Study_v1.1
- 10天用verilog实现MIPS_cpu，内有清晰结构图。很好的cpu设计学习资料！-10 days with verilog achieve MIPS_cpu, within a clear structure diagram. Good cpu design learning materials!
MIPSCPU
- 这是verilog实现的MIPS多周期CPU在modelsim下面仿真通过-This is achieved verilog CPU MIPS multi-cycle simulation in modelsim below by
cpu5.10_modelsim
- 用verilog编写的8位最简cpu代码，能实现简单的加减运算，存储运算，以及寄存器操作。-Verilog prepared with 8 simple CPU code, to achieve a simple addition and subtraction, memory operations, as well as register operations.
cpu-7-verilog
- 多周期cpu设计asadsdddasd-multi cpu design
CPU
- 用Verilog实现的 哈佛结构的简单指令集CPU程序，由ALU、地址译码器、指令译码器等部分组成-Part of a simple instruction Verilog realize the Harvard architecture CPU program set by the ALU, address decoder, an instruction decoder, etc.
CPU-master
- 单周期CPU的Verilog源码实现，基于Vivado(Single cycle CPU Verilog source code implementation, based on Vivado)