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pipeline
- 用Quartus II 设计的3级流水CPU,指令采用二次重叠执行方式-Quartus II design with three-stage pipeline CPU, instruction execution overlaps with the second time
CPU
- 在THINPAD平台上的50M时钟5级流水支持THCOMIPS指令集的CPU,并附带8核扩展,内有详细实验报告。全部用VHDL编写,并附有样例验证程序,开发环境为ISE 14.1。-Water support THCOMIPS instruction set CPU 50M clock the THINPAD platform 5 and comes with an 8-core extension, within a detailed test report. All written usin