基于wishbone的字符型lcd core，支持16×2的字符型lcd显示，verilog语言编写-character lcd core based Wishbone bus, support for 16 × 2' s character lcd display, verilog language

verilog在1602上顯示時間，並可以調時間，整點報時-verilog display the time in 1602, and can adjust the time, the whole point timekeeping