The design of the All Digital FM Receiver circuit in this project uses Phase Locked Loop (PLL) as the main core. The task of the PLL is to maintain coherence between the input (modulated) signal frequency,iωand the respective output frequency,oωvia p

实现了单片机AT89C51与CPLD之间的双向通信含有可编程逻辑器件发送数据到单片机的VHDL源程序和CPLD接收VHDL源程序-AT89C51 microcontroller and CPLD achieve a two-way communication between the programmable logic device containing a microcontroller to send data to the receiver VHDL source code and CPL