Turbo码编码器的删除模块，此模块是CCSDS标准系的码率为1/2和1/3的删除模块-Turbo code encoder to delete module, this module is the Department of CCSDS standard rate of 1/2 and 1/3 of the delete module

24秒计时器的FPGA实现，分三个模块并内分别附上VHDL程序(24-second timer FPGA implementation)