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mid-filter
- 用vhdl语言实现的中值滤波,硬件需要DE2板
fft
- 基于FPGA实现快速中值滤波，有效果显示，实现简单
median-filter
- 基于FPGA的图像中值滤波算法的优化及实现vhdl-中值滤波 利用VHDL语言实现三级流水线中值滤波-FPGA-based image filtering algorithm optimization and realization of vhdl-median filter using VHDL language three pipelined median filter
medianfilter
- 图像滤波中的中值滤波，有效滤除椒盐噪声，使用verilog语言编写-Image filtering in the median filter, effectively filter out salt and pepper noise, using verilog language
median
- 用verilog编辑的中值滤波器！语言旁表有注释方便理解！-Using Verilog editor median filter! Language beside the table annotated to facilitate understanding!
MedFilter_VHDL
- 用VHDL实现了Matlab中MedFilt1函数3阶中值滤波。进行排序时没有用软件使用的排序法，而是通过简单的比较实现。-VHDL implementation using the Matlab function MedFilt1 of 3-order median filter. Sort of no use when the software used to sort the Law, but through a simple comparison of implementation.
median_filterCode
- 采用快速中指滤波算法实现图像的中值滤波，使用VHDL语言ISE环境-Image Median Filter
mid_filter
- 中值滤波的实现，用于图像的预处理。取出图像噪声-Implementation of median filter for image preprocessing. Remove image noise
3-3-median-filter
- verilog编写的适用于fpga的3x3模板中值滤波-verilog fpga prepared for the 3x3 median filter template
Code_for_MedianFilter33
- 包含边缘探测的中值滤波FPGA工程，分辨率1024x16-Contains the edge detection filter in the value of the FPGA project
msk_mod
- msk 调制解调源码，每符号采样8次。对pn码进行调制后，进行解调，解调过程含：符号差分，中值滤波等过程。-msk modem source code, sample 8 times per symbol. Modulation of the pn code after the demodulation, the demodulation process including: symbol differential, the value of the filtering process.
mid-filter
- mid-filter 中值滤波算法的原理及核心代码 word版-mid-filter median filter and the core principles of the code word version
5354
- 图像的中值滤波算法及其FPGA实现Image median filtering algorithm and its FPGA implementation-Image median filtering algorithm and its FPGA implementation
mid01
- 中值滤波的VHDL语言，包括所有的工程，工程中包含所有的模块程序-Median filtering VHDL language, including all engineering, engineering program contains all the modules
eetop[1].cn_Code_for_MedianFilter33
- 本程序实现3*3中值滤波的Verilog语言编写-This procedure achieved 3* 3 median filter Verilog language
filter
- 用vhdl硬件描述语言写的中值滤波器，主要对尖峰脉冲进行消除。在fpga上实现。-Vhdl hardware descr iption language used to write the median filter, mainly to eliminate spikes. Implemented on the fpga.
zzlB
- QUARTUSII 9.0 下的三级流水线中值滤波工程，vhdl源程序等。可用于fpga做图像预处理。-the three stage pipeline median filter project under QUARTUSII 9 , VHDL source program. which can be used by FPGA to do image preprocessing.
all_MedFilter_VHDL
- 本文介绍了中值滤波算法的FPGA详细实现，很详细，很全-This article describes the median filter algorithm to achieve the FPGA detailed, very detailed, very full
图像中值滤波FPGA实现V1.0
- 实现图像的中值滤波功能，文件里有效果展示(The realization of the median filter function of the image, the file has the effect of display)