恢复以曼彻斯特编码格式输入的mdi信号成实际数据并存储在双端口RAM后以中断方式通知DSP读取数据，所需双端口RAM程序可以从相应的FPGA编译系统中产生-A return to the Manchester encoded signal is input into the actual data mdi and stored in the dual-port RAM notify the DSP after the break to read the data, the required du

usb2.0开发的一些实例，利用端点中断进行环路测试，上位机控制LED，通过自定义请求存取外部RAM等测试工程-usb2.0 development with some examples, the use of endpoint interrupt loop test, PC control LED, through custom request access to external RAM, test engineering

PCI总线芯片PCI9054本地总线的FPGA控制逻辑。 硬件架构为PCI9054+双口RAM+FPGA。 使用USERo清中断。 该逻辑以在项目中应用。-PCI bus FPGA chip PCI9054 local bus control logic. Hardware architecture PCI9054+ dual-port RAM+ FPGA. Use USERo clear interrupts. The logic to apply in the pro

串口接收数据校样后存入双口ram,接收完整帧数据后，置中断，通知串口发送-After receiving proof serial data stored in dual port ram, receive a complete frame of data after the interrupt, serial port to send notifications