搜索资源列表
NAND01GR3B_VH1
- nand flash NAND01GR3B (st)的仿真模型 (VHDL) 的-nand flash NAND01GR3B (st), the simulation model (VHDL)
71V416_Verilog_95461.rar
- SRAM IDT71V416的VerilogHDL仿真模型源码文件,SRAM IDT71V416 simulation model of the source document VerilogHDL
Micron_SDRAM_DDR2Simulation_mo
- DDR2 SDRAM仿真模型,适合于ModelSim下工作,请先阅读readme,DDR2 SDRAM Simulation Model which is suitable for modelsim. Please read readme file firstly.
cy7c1371c_vhdl_10.zip
- cy7c1371c ZBT SRAM 的仿真模型,VHDL编写。,the simulate model of cy7c1371c,VHDL language.
MT29FxxG08xx.rar
- MT的NAND FLASH MT29FxxG08xx系列的Verilog仿真模型,包含详细说明,试验证明,非常准确。,MT of the NAND FLASH MT29FxxG08xx series of Verilog simulation model, contains a detailed descr iption, testing proved very accurate.
NAND-FLASH
- flash 仿真模型,自己看吧-flash simulation model
sdram 仿真模型
- sdram 仿真模型,用于verilog代码sdram行为级仿真-sdram modelsim model
verilog_sdram_controller_testbench
- SDRAM 控制器 ,Verilog版本的,带有完整的SDRAM 仿真模型,testbench等,能够实际使用,并且利于学习-The SDRAM controller is designed for the Virtex V300bg432-6. It s simulated with Micron SDRAM models. The design is verified with backannotated simulation at 125MHz
micron_sdram_simulation_model
- micron各种规格的SDRAM的仿真模型及详细设计资料,基于verilog语言。-micron variety of SDRAM simulation model and detailed design information, based on the verilog language.
IS63LV1024L
- ISSI SRAM IS63LV1024L 时序仿真模型-Verilog model of IS63LV1024L
2048Mb_ddr2
- DDR2 仿真模型 DDR2 仿真模型-DDR2 Simulation Model
sdram_models
- MICRON公司SDRAM的各种仿真模型,可以用于各种仿真环境-sdram simulation model
m73a_nand_model
- Micron公司m73a系列nand flash仿真模型及测试文件-micron m73a series nand flash simulation model and testbench
07_SMP8634_IBIS_rev10_released
- 高清多媒体播放器芯片smp8634的ibis仿真模型-High-Definition Multimedia Player The SMP8634 chip of ibis simulation model
ddr_sdr_V1_1
- DDR控制器 - 用XILINX Virtex II FPGA实现 - 使用DDR MT46V16M16作为仿真模型 - 通用化-DR SDRAM Controller Core - has been designed for use in XILINX Virtex II FPGAs - works with DDR SDRAM Device MT46V16M16 without changes - may be easily adapted
sdram
- 程序说明: 本次实验控制开发板上面的SDRAM完成读写功能。 先向SDRAM里面写数据,然后再将数据读出来做比较,如果不匹配就通过LED变亮显示出来,如果一致,LED就不亮。 part1是使用Modelsim仿真的工程 part2是在开发斑上面验证的工程 目录说明: part1: part1_32是4m32SDRAM的仿真工程 part1_16是4m16SDRAM的仿真工程 \model文件夹里面是仿真模型 \rtl文件夹里面是源文件 \sim文
IS64LV6416L
- Asynchronous SRAM IS64LV6416L modelsim仿真模型-Asynchronous SRAM IS64LV6416L Verilog model
IS61LV10248
- IS61LV10248器件的modelsim 仿真模型-IS61LV10248 Verilog model for modelsim
mt48lc4m32a2
- SDRAM mt48lc4m32 的modelsim门级仿真模型- modelsim gate-level simulation model for SDRAM mt48lc4m32