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verilog-hdl
- VHDL的各种算法算例，可供西电的大作业设计参考，是学习可编程语言的必备算例-VHDL examples of various algorithms available for Western Electric' s big job reference design is essential to learn a programming language examples
add
- 北京邮电大学VHDL课程作业，基于xilince ISE试验箱开发的，可以做简单的半加器加法-Beijing University of Posts and VHDL course work, based xilince ISE chamber developed, can do simple addition of half-adder
rili
- 北邮的大作业，基于ISE试验箱编程的万年历，LCD数码管显示，可以开关控制，测试成功-Great job BUPT, based on the ISE chamber programming calendar, LCD digital display, you can switch control, the test is successful
12061226project8
- 基于VHDL的多周期cpu模拟，北航作业，已检测可以运行。-cpu simulator
cpu_1
- 用verilog设计五级CPU的框架，需要自己另行补充指令，可作为学生作业和训练内容-Five CPU with verilog design framework, needs its own separate supplemental instruction can be used as student assignments and training content
washmashine
- 用VHDL实现的洗衣机作业，可以启动、清洗、排水、脱水、换档。-Washing machine with VHDL, you can start, wash, drain, dehydration, shift.
jisuan
- 4*4键盘输入实现加减乘的计算器，数电实验大作业，下到FPGA实验正确。-4* 4 keyboard input to achieve modified by the calculator, the large number of electrical test operations, right down to the FPGA experiment.
8bits
- 用Verilog语言模拟的8位优先编码器，可作为课堂作业实用，是完整工程代码-Using Verilog language simulation of the 8 priority encoder, can be used as a classroom operation, is a complete code
Binary-BCD-code
- 用Verilog语言写的二进制转BCD码,可以作为课堂教学实验或者课后作业，有完整工程代码-Written in Verilog language transfer binary BCD code, can be used as a teaching experiment or the homework, a complete project code
Four-input-static-display
- 用Verilog语言写四位静态输入显示，可做课堂实验后课后作业，有完整代码-Written in Verilog language, according to the four static input to do homework after class experiment, has a complete code
alu
- 这是一个alu源代码，是大学数字电路课的实验课作业。-this is a alu code.
cpu_hazard
- cpu的开发流程，包括hazard的处理，我课程作业的大作业，还是有参考价值的-cpu development process, including the hazard of handling large jobs my course work, or a reference value
hit_the_block
- 数字逻辑课程大作业，使用verilog语言编写的打砖块游戏。通过FPGA按钮控制弹板移动，反弹小球，控制小球方向，击打砖块。有VGA模块。-Digital Logic Courses big operations, the use of Verilog language brick game. The FPGA button controls the movement of the board, bounces the ball, controls the direction of the ba
piano
- 电子琴 原创 作业 VHDL 采用计数器分频，内含简单儿歌数首，爱迪克ＥＤＡ实验箱，有数码管与ＬＥＤ显示，采用键盘式输出，两行，中音高音。(Electronic piano original work VHDL, using counter frequency division, contains a few simple nursery rhyme, Edik EDA experimental box, there are digital tube and LED display, usin
gate2
- 二输入门代码，作业学习，数字逻辑电路答案条件好多(the ppt for study very very good)
cpu2
- 这是在vivado平台上编写的多功能流水线cpu的实现，是我们课程实验的大作业(This is the implementation of the multi-functional pipelined CPU written on the vivado platform. It's a big job for our course experiment.)
chuzujifei
- 使用Quartus II 9.0编写的出租车计费系统源码，是课程设计大作业验证通过，可以直接仿真验证(The use of Quartus II 9 written taxis charging system source code, is the course design of large work verification through, can be directly simulated and verified)
Single_cpu
- 单周期CPU自己课程大作业做的，亲测好用，verilog语言，适用vivado(Single cycle CPU course to do, pro - use, Verilog language, suitable for vivado)
Multi_cpu
- 多周期CPU自己课程大作业做的，亲测好用，verilog语言，适用vivado(Single cycle CPU course to do, pro - use, Verilog language, suitable for vivado)
NEW
- Verilog投币式手机充电仪 清华大学数字电子技术基础课程EDA大作业。刚上电数码管全灭，按开始键后，数码管显示全为0。输入一定数额，数码管显示该数额的两倍对应的时间，按确认后开始倒计时。输入数额最多为20。若10秒没有按键，数码管全灭。(Verilog coin operated cell phone charger EDA major homework of digital electronic technology foundation course, Tsinghua Un