搜索资源列表
DDSsheji
- 再发一个修改的完善的基于FPGA的DDS信号源实现方案-Recurrence of an amendment to improve the FPGA-based realization of the DDS signal source program
digital
- 多功能数字钟的VHDL源代码。多功能数字钟具有的功能:显示时-分-秒、整点报时、小时和分钟可调等基本功能。钟表的工作是在1Hz信号的作用下进行,每来一个时钟信号,秒增加1秒,当秒从59秒跳转到00秒时,分钟增加1分,同时当分钟从59分跳转到00分时,小时增加1小时。-Multifunction digital clock VHDL source code. Multi-function digital clock with functions: display- minutes- seconds
DDS
- 直接数字信号源的源代码和发生器的设计报告-Direct digital signal source code and design report
sin_gnt
- 用FPGA实现的正选信号发生器,可以用于后续实验的信号源-sin_gnt
frequency
- 基于XILINX平台设计的数字频率计,在FPGA内部设计信号源,产生100KHz方波,板上数码管用于显示被测信号频率,并显示6位有效数字,实现对TTL电平的测试,测量精度为10Hz。-: The digital frequency meter based on XILINX development terrace generates 100 KHz square waves by a supply oscillator within FPGA. The nixietubes of the boa
mcu-fpga
- 目录 FPGA & MCU 开发板介绍 实验1 QuartusII 软件应用 实验2 Keil C51 应用 实验3 字符型LCD YM1602 的应用 实验4 带字库的中文LCD YM12864 的应用 实验5 时钟芯片DS1302 的应用 实验6 I2C 总线器件AT24C64 的应用 实验7 数字温度传感器的应用 实验8 行列式键盘 实验9 硬件电子琴的设计 实验10 AD 与DA 的使用 实验11 简易DDS 信号源设计 实验12 用模
Digital_Phase_Measurement
- 测量相位差并用LCD显示。从信号源接入两路信号,经过AD1和AD2转换后,送入FPGA中。 在FPGA中,使用双值法整形,得到两路标准的方波,然后测出两路信号的时差Δt,以及信号的周期T, 并计算相位差(ΔΦ=Δt/T*360°)。并送入1602中显示。经测试,其测相误差小于1 。-Measured phase difference and with LCD display. Two-way access from the source signal, converted by AD1
signal_gaojindu
- 信号源的verilog代码,已经调试通过,很有参考价值-verilog code of signal source
signal
- verilog写得一个信号源,很爽的,输出667hz信号超级准-verilog write a signal source, so cool, and the output signal is super-quasi-667hz
audio-signal-analyzer
- 一等奖作品:音频信号分析仪的FPGA源码,真的不错-First prize works: audio signal analyzer FPGA source code, really good
esi
- FPGA的涡流检测正交信号源的设计方法 .-Eddy current testing FPGA design method of orthogonal signal
AD9850
- 关于扫频信号源的程序 使读者更清楚地了解扫频信号源的功能及应用-Procedures on the sweep signal to sweep the reader a clearer understanding of the function and application source
FPGA-DDS
- 直接数字频率合成器,产生频率可控的信号源。-Direct digital frequency synthesizer to generate controlled frequency source.
DDS
- 实现了基于FPGA的DDS信号源设计,能同时两路输出,输出波形包括正弦波、三角波、方波和锯齿波,且其频率和相位均可调,还能计算两路输出信号的相位差。-FPGA-based implementation of the DDS signal source design, two outputs simultaneously, the output waveforms including sine, triangle, square and sawtooth waves, and its freque
DDS
- VHDL dds信号源产生 很有查考价值-VHDL signal waveform signal generator DDS produced
DDS_PHASE
- 基于DDS BUILDER和VHDL写的数字移相信号源,经DA实测760Hz波形良好,手里没有高速DA,未能继续测试。仅供参考-DDS BUILDER and VHDL-based digital phase shift number written sources, 760Hz waveform measured by the DA good hands there is no high-speed DA, unable to continue testing. Reference
frequency_measure
- 关于用FPGA测量数字信号源频率的源代码。 用的是verilog语言-Measured using FPGA digital signal on the frequency of the source code. Using verilog language
phase_measure
- 关于用FPGA测量数字信号源相位差的源代码。用的是verilog语言-FPGA on the use of digital signal phase difference measurement of the source code. Using verilog language
plj_book
- EDA,verilog 语言写的频率计,一个是测频,一个是产生一定的频率作为信号源,可在cycloneII 上验证,-EDA, verilog language written in frequency counter, one frequency measurement, one is a certain frequency as the signal source can be verified on the cycloneII, thank you! !
xinhao
- 实用信号源的设计与制作参考资料(AD9851 DDS芯片,含源程序)-Practical source of design and production of reference (AD9851 DDS chip, including source code)