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XUELIEXINHAOFASHENGQI
- 基于ALTERA MAX系列FPGA的开发板的序列信号发生器源码。应该可以通用。设计环境为QUARTUS II。压缩包包含整个工程。-ALTERA MAX Series FPGA-based development board serial signal generator source. Should be universal. Design environment QUARTUS II. Archive contains the entire project.
buzzer_sos_2
- 用verilog产生“SOS信号”，就是有次序的控制输出莫斯密码的“点”，“画”和“间隔”。一个比较好玩的源码。-Produce " SOS signal" with verilog, is to have control of the output sequence Moss password " point" , " painting" and " interval." A more fun source.
dtrigger
- 分频器，对输入时钟进行分频,可以用来驱动电机，或者用作其他需要时钟源的外设的驱动信号-Divider, devide the input clock frequency to another frequence clock signal
ov7670
- OV7670驱动代码（源码） 只为驱动代码，输出为像素点信号，必须有相应的下层模块才能完全完成对摄像头的控制-OV7670 driver code (source) only for the driver code, the output pixel signal, there must be a corresponding lower module to fully complete camera control
I2C
- I2C控制源码 用于摄像头的信号传输和控制。 在使用时FPGA需要接上上拉电阻否则无效-I2C control source signal transmission and control for the camera. When using the pull-up resistor connected FPGA requires otherwise invalid
DE2_video_pass_demo-rww
- 视频发射源发射信号，基于DE2115fpga平台的视频信号显示与处理-Transmitting the video signal transmission source, based on a video signal display DE2115fpga platform and processing
CD-ROM-code-(verilog-hdl)
- 数字信号处理的fpga实现 第2版-光盘源码（verilog HDL）-Fpga implementation of digital signal processing 2nd Edition- CD source (verilog HDL)
Experiment08
- FPGA源码，供初学者使用，时钟化和信号长度-GA source code, for beginners, clock and signal length
UNI-T_signal
- 普源示波器自带信号测试版，CPLD实现，产生方波、三角波、锯齿波等信号-RIGOL signal beta, CPLD implementation, generate a square wave, triangle wave, sawtooth and other signals
Low-Power-FIR-Filter
- FIR滤波在数字信号领域中很大作用。这个源码很大帮助VHDL工程师或学习者。里面包含说明书。-This report investigates the power consumption of digital arithmetic circuits for use in the design and implementation of a 15-tap programmable Finite Impulse Response (FIR) filter.
DDS
- DDS的核心是相位累加器，相位累加器有一个累加器和相位寄存器组成，它的作用是再基准时钟源的作用下进行线性累加，当产生溢出时便完成一个周期，即DDS的一个频率周期。加载Matlab 产生的波形，通过FPGA输出DDS信号-Core DDS is the phase accumulator, a phase accumulator and phase accumulator registers, its role is to carry out a linear accumulation under
frequency-demultiplier
- 电子分频器：有源电路，位于功率放大器之前，将前置音频信号分频后再用各自独立的功率放大器，把每一个音频频段信号给予放大，然后分别送到相应的扬声器单元-Electronic frequency divider: active circuits, in front of the power amplifier, will lead audio signal frequency and then separate the power amplifier, the every audio frequenc
verilog
- 数字信号处理的FPGA实现(第3版) verilog源码-FPGA digital signal processing (3rd Edition) verilog source
m
- 为随机序列产生器，可以作为调制信号的信源-As the random sequence generator, can be used as a modulation signal source
of
- VHDL源码OFDM信号传输系统基于FPGA(Field-Programmable Gate Array)-VHDL source OFDM signal transmission system based on
verilog
- 《数字信号处理的FPGA实现（第三版）》作者：U.Meyer-Baese 的配套源码，基于quartus9.0编写，使用的cyclone ii。其中包含FIR IIR FFT等算法的实现，对学习图像处理很有帮助。- FPGA digital signal processing (third edition) Author: U.Meyer-Baese The matching source, based on quartus9.0 preparation, the use of cyc
vhdl
- 《数字信号处理的FPGA实现（第三版）》作者：U.Meyer-Baese 的配套源码，基于quartus9.0用VHDL编写，使用的cyclone ii。其中包含FIR IIR FFT等算法的实现，对学习图像处理很有帮助。- FPGA digital signal processing (third edition) Author: U.Meyer-Baese The matching source, based on quartus9.0 prepared using VHDL, t
DDS
- 信号发生器设计 信号发生器由波形选择开关控制波形的输出, 分别能输出正弦波、方波和三角波三种波形, 波形的周期为2秒（由40M有源晶振分频控制）。考虑程序的容量,每种波形在一个周期内均取16个取样点,每个样点数据是8位(数值范围:00000000~11111111)。要求将D/A变换前的8位二进制数据（以十进制方式）输出到数码管动态演示出来。-Signal generator design The signal generator is controlled by waveform se
2_Mixer
- 基于Quartus II 13.0 的将两信号进行混合相乘的源码，适合于新人熟悉掌握该软件使用-Based on the Quartus II 13.0 mix two signal multiplication of the source code, suitable for a new master to use the software
FPGA_USB2.0设计
- 把FX2配置成从FIFO的模式， 配置为单片机工作时钟24M，端点2输出，字节1024，端点6输入，字节1024，信号全设置为低电平有效等。我们的模块驱动时钟我们配置成内部输出时钟，也就是让FX2给我们的设计当做时钟源，输出一个最大的配置时钟48M的时钟。(The FX2 is configured from FIFO mode, configured as MCU working clock 24M, endpoint 2 output, byte 1024, endpoint 6 input